Suppose an i2S DAC is fed audio signals from a dedicated RAM which is filled with audio data after the main CPU decompresses it. The data would be streamed directly from the RAM without the need of a complex processor, and the only clock pulses would be those controlling the DAC. All this would be on a dedicated PCB. This card would receive commands like to load a stream to its RAM, to clear such a stream from its RAM, to start playing, to stop playing, to pause and to change volume.
Since large RAM chips are dynamic, I see a problem though, and this is, when the onboard RAM receives refresh pulses. During this instant, a static RAM has to be used. Alternatively, data would be read from the onboard RAM, stored in a static RAM and fed to the onboard DAC. The issue of refresh cycles can also be solved by double buffering to two static RAM chips which are refreshed at different times.
Since large RAM chips are dynamic, I see a problem though, and this is, when the onboard RAM receives refresh pulses. During this instant, a static RAM has to be used. Alternatively, data would be read from the onboard RAM, stored in a static RAM and fed to the onboard DAC. The issue of refresh cycles can also be solved by double buffering to two static RAM chips which are refreshed at different times.
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Old-fashioned DRAMs (both the ordinary and the EDO type) could be refreshed by simply accessing each row often enough. (Or was it each column? I think row, but it was two decades ago that I last built something involving DRAM.) I haven't a clue if that still works with SDRAMs.
This is basically a Fifo which exists in a number of version.. Ian (long), DAM (short) upcoming Andrea (long?)....
I don't see the gain of a big RAM disc... why, one still need a memory controller and some glue logic between the RAM handler and the i2s.
You describe an implementation - what aspect / characteristic is this ment to improve?
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I don't see the gain of a big RAM disc... why, one still need a memory controller and some glue logic between the RAM handler and the i2s.
You describe an implementation - what aspect / characteristic is this ment to improve?
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I think that what you are describing is achieved by using the host to DAC in asynchronous mode so the precision of the clock in the DAC is in charge. SOP in the studio world is using a master clock.
This is why we have simple buffers in the IO channel.
This is why we have simple buffers in the IO channel.
SDRAMs are smart, they do everything really neatly, I'd recommend reading up about them, particularly burst modes. So long as you regularly access them they sort out the refresh automatically. I've done a few projects using SDRAM chips pulled from old PC100 DIMMs. One problem you might have is the minimum clock speed - I2S is pretty glacial compared to 100MB/s. Most SDRAM chips are only guaranteed above 1MHz, and even 192k stereo at 32 bits only needs 1.5MB/s
The last thing I built involving the kind of chips you normally find in personal computers was a field memory recorder for the local radio station Haarlem105 that I made between 1997 and 2000. It was an 8 MHz CMOS Z80 system connected to two 32 MB EDO DRAM modules and a Cirrus Logic CS4236 CODEC chip that was normally used on ISA sound cards, plus a microphone amplifier with a limiter that you could not switch off and some switches and an LCD module as user interface.
I actually wanted to use a CS4231, but it was not available anymore. The CS4231 was a normal ISA chip and the CS4236 an ISA plug and play chip, so I had to mimic the plug and play algorithm to get the CS4236 to work - far more complicated than using a CS4231 would have been.
I chose EDO DRAM modules because they were readily available and cheap, but by the time I had finished, they had gone obsolete, because everyone had switched to SDRAM.
Needless to say, the CS4236 had also gone obsolete, as ISA plug and play had been replaced with PCI.
So long story short: if your timing is as bad as mine, there is no point in reading up on computer chips, as they will be obsolete by the time you have finished reading.
I actually wanted to use a CS4231, but it was not available anymore. The CS4231 was a normal ISA chip and the CS4236 an ISA plug and play chip, so I had to mimic the plug and play algorithm to get the CS4236 to work - far more complicated than using a CS4231 would have been.
I chose EDO DRAM modules because they were readily available and cheap, but by the time I had finished, they had gone obsolete, because everyone had switched to SDRAM.
Needless to say, the CS4236 had also gone obsolete, as ISA plug and play had been replaced with PCI.
So long story short: if your timing is as bad as mine, there is no point in reading up on computer chips, as they will be obsolete by the time you have finished reading.
Well I have no shortage of old SIMMs and DIMMs in the drawer from memory upgrades
way back when... I can't be the only one.
way back when... I can't be the only one.