Can't turn FLT on HIGH on GY-PCM5102

[steven59]

Hello,

I am spending hours to put FLT (low latency) on high on GY-PCM5102 card (see attached). As mentionned on the datasheet, I tried to connect FLT on 3v3 but the card stop itself, with 10k resistor nothing change, checked with RTL utility. Do you have an idea of what going wrong ? Thank you

 

[Markw4]

Maybe wise to sketch up a schematic of the board including jumper settings on the back. That way there would be something to help us better understand what might be the cause.

Other than that it might be useful if there is a scope to look at incoming digital signal timing.

 

[steven59]

Maybe wise to sketch up a schematic of the board including jumper settings on the back. That way there would be something to help us better understand what might be the cause.

Other than that it might be useful if there is a scope to look at incoming digital signal timing.

After more investigation I found that FLT is linked with the 1st pad, "1" was factory set on L (LOW, so FIR according to datasheet), just had to desolder to put 1 on H (HIGH so IIR).

I expected with this setting make this dac sound more close to my old tekdevice tda1387 (passive I/V). I'm a bit disappointed, even if the BB is superior in details, instrument separation, spacialisation and perceived dynamic, the timbre is still not on par, it doesn't sound as natural as my NOS dac (even after tweaking with sox). This dac is fed with xingcore usb interface and AS-318B clock. I think I'm becoming picky 😳

 

[Markw4]

Can you provide a pic showing how I2S is wired to the dac board? Is it treated as sensitive, impedance-controlled RF transmission line?

Also it may help to use a low noise dedicated voltage regulator for AVDD, possibly one with not overly-stiff regulation, and with the regulator located very near the dac chip.