Hi guys,
i am currently creating a small Wifi Amp. I want to ask if someone can review my Schematic. The Board itself does work already. Rev.2 i currently in progress. I changed the DCDC to something with a higher Frequency. Do you have some Ideas or Improvements?
Rev 2:
i am currently creating a small Wifi Amp. I want to ask if someone can review my Schematic. The Board itself does work already. Rev.2 i currently in progress. I changed the DCDC to something with a higher Frequency. Do you have some Ideas or Improvements?
Rev 2:
- Via stitching for ground plane
- DC/DC to higher Frequency
- Route the output signals on one layer [without Vias, if possible]
- PBTL Jumper
- More Via for audio line
- Add better cooling vias for the amplifier IC, it overheats, improve thermals with a proper ground plane
- Switch the Power regulator (XC6220)
- Remove the unnecessary logic level converter
- Implement reverse polarity protection
- LED: WS2812B
- Change layout, from left to right: DCDC ESP32 AMPLIFIER, and not DCDC AMPLIFIER ESP32, or move the dcdc to the bottom right far away from the amplifier.
Very nice! If I read the schematic correctly, you tied MCLK to BCLK, and was going to suggest an option to receive MCLK from the ESP32. However, I just noticed that Infineon released a updated datasheet for the MA12070p. The revision page now states the following...
Silicon update. Improve of DC offset in BTL, PBTL and 2.1 configurations. Correction of known issues and limitations in errata sheet v1.0 in sections 1.1, 1.2 and 1.4.
Show power mode profile 5 value as “101” in 0X1D register address.
Show channel disable register 0x07.
Running the DAC directly from the MCLK is not supported, delete functionality.
Amplifier gain modification is not supported, delete register.
Does that second to last sentence mean the revised chip will no longer accept an external MCLK?
Hey guys...
Randomly stumbled upon this thread in google and just had to create an account to answer this one in case other people will find it useful. Also, I work in the Merus Audio team in Infineon as an application engineer. I should have a different diyaudio account hidden somewhere but I think it's tied to my old e-mail address 10+ years ago so I think it's lost.
Anyway, MA12070P does not need master clock (MCLK) to function. It just needs a bit clock (BCLK) which is then fed to the CLK input (MA12070P's master clock) and also the SCK input (bit clock input).
If anyone stumbles upon this like I did, I also want to mention that audio IC questions for Infineon's products, e.g. MA12070P in this case, can be asked on the dedicated forum found here: https://community.infineon.com/t5/Class-D-Audio-Amplifier-IC/bd-p/classdaudio
I hope this helps
(and sorry for reviving this old thread 🙂 )
Oh! And very nice board, Daniel! I like it!