Hi folks, I have a courtesy to ask if possible. I have some J-FETs to test which are 2n3819, MPF102 and 2N5670, and I have the less noisy ones because they have to amplify very low signals from 10 to 100 microvolt. I would initially need a scheme to test the gain and noise and then create a multistage with the less noisy ones chosen. I have tried several circuits on LTSpice with their libraries but the result does not convince me. For example that the output sine does not have the 0 volt offset voltage. Then the gain is low. Maximum G = 1 or 2. What do you think?
Although this has much higher maths if you scroll down you will find a J-Fet noise test circuit .
Sorry I have no LTSpice software installed but stopped at practical /analog test gear some of which I built myself .
newest.dvi - JFET_Noise.pdf
Sorry I have no LTSpice software installed but stopped at practical /analog test gear some of which I built myself .
newest.dvi - JFET_Noise.pdf
Hi duncan2, thanks for the PDF. I ask another question. On the datasheets what is the value that indicates the noise of the J-fet if present? I have several J-Fet is a value that is also useful for me to understand the input sensitivity should be the Gate Current (Ig). That is, the lower this value, the more sensitive the J-Fet is. In the meantime I also did some tests with LTSpice that actually based on the data it has, it is capable of calculating the noise (at least on paper). In simulations with some of the most famous fetes I found incredible differences in noise (Open circuit with no load. If closed the noise drops). I used a very high bandwidth because I recycled a circuit from another scheme. I attach some screenshots as an example. Obviously we are talking about inaudible noise on every single component which however increases in the case of array or multistage if I'm not mistaken. Also for this reason I am interested in noise. Obviously there is certainty with the real test. The fact is that very often on this simulator once the circuits are finished I get low gain values or the voltage offset is not at zero as I would expect. . This happens with many of the patterns I found and they are really simple. Maybe I expect a different result from what can be obtained from these components?
