Hi!
Is there anyone that knows how to build a SMPS with the SG3525 that has some kind of protection against the staircase saturation that occurs in push-pull converters. I know that I could use a current controlled power supply, but I want to use a voltage controlled power supply.
/Micke
Is there anyone that knows how to build a SMPS with the SG3525 that has some kind of protection against the staircase saturation that occurs in push-pull converters. I know that I could use a current controlled power supply, but I want to use a voltage controlled power supply.
/Micke
for low voltage application, it's always sufficient to use SG3525 inherent functions to help avoid core saturation.
First, install 'deadtime' resistor between pins 5 and 7, define its value from diagram in SG3525' datasheet so that to keep deadtime about 1us or higher. Another way is to use timing capacitor over 5nF (see same diagram there).
Second, use 0,1uF capacitor from pin 9 to ground (pin 12), this will limit feedback response time so that pulse width will change rather slowly in typical application (25-100 kHz no such problems in my practice).
Hope I've been helpful.
First, install 'deadtime' resistor between pins 5 and 7, define its value from diagram in SG3525' datasheet so that to keep deadtime about 1us or higher. Another way is to use timing capacitor over 5nF (see same diagram there).
Second, use 0,1uF capacitor from pin 9 to ground (pin 12), this will limit feedback response time so that pulse width will change rather slowly in typical application (25-100 kHz no such problems in my practice).
Hope I've been helpful.
I think there is need for SG3525' math model rather for theoretical researches.
All functions are described well in its datasheet and, yes, it works pretty according to papers and diagrams 😀
Besides there's a lot of schematics of any kind on the Web with this chip.
All functions are described well in its datasheet and, yes, it works pretty according to papers and diagrams 😀
Besides there's a lot of schematics of any kind on the Web with this chip.
How can I eliminate the staircase saturation whit just increasing the dead time to 1 us or higher. Or adding a capacitor between pin 9 and 12. Wouldn’t I need some kind of feedback from the primary side to be able to compensate for the in balance of flux density?
I know that if I would use a current control the staircase saturation is no longer a problem.
The problem is that I do not fully understand how current mode control operates.
I know that you are monitoring the current on the primary side and then the current have reached a specified level the pulse is terminated. Since the current on the primary side increases laniary I would be able to calculate the voltage on the secondary side if the load is constant.
But if the load on the secondary side not is constant that happens then? Do the voltage changes whit the load or do it remain the same any way?
I think it works like this but I’m not sure.
For instance if the load gets higher so that the current on the secondary side decreases do the core then get more saturated? And if the core gets more saturated that would mean that the current on the primary side faster reaches the terminating level.
Am I correct or have misunderstand it completely.
I know that if I would use a current control the staircase saturation is no longer a problem.
The problem is that I do not fully understand how current mode control operates.
I know that you are monitoring the current on the primary side and then the current have reached a specified level the pulse is terminated. Since the current on the primary side increases laniary I would be able to calculate the voltage on the secondary side if the load is constant.
But if the load on the secondary side not is constant that happens then? Do the voltage changes whit the load or do it remain the same any way?
I think it works like this but I’m not sure.
For instance if the load gets higher so that the current on the secondary side decreases do the core then get more saturated? And if the core gets more saturated that would mean that the current on the primary side faster reaches the terminating level.
Am I correct or have misunderstand it completely.
Looks like you have read too much theory 🙂 Simple prove that it works is millions of amplifiers in the world that include the same push-pull center tap SMPS (among them are thousands of my design using SG3525 if it helps to affirm the prove 🙂 )
Diving back into theory - correct me if I confuse those things - capacitor to ground on the error comparator output (SG3525 pin 9) slows down pulse width changing (very slightly during one cycle), helping to avoid rapid non-symmetry in core flux. Deadtime between pulses helps core magnetic flux to "reset" to initial value each half cycle. If you don't have voltage regulation, that is no feedback (it is the most common case), then most of the time pulse width is maximum - trust the chip making pulses with exactly same length - and changing only at start-up.
Another popular chip is TL494, not much difference in circuitry, operation principles the same.
Anyway, why so much talking and doubts, just try it and enjoy the reality 😀
Diving back into theory - correct me if I confuse those things - capacitor to ground on the error comparator output (SG3525 pin 9) slows down pulse width changing (very slightly during one cycle), helping to avoid rapid non-symmetry in core flux. Deadtime between pulses helps core magnetic flux to "reset" to initial value each half cycle. If you don't have voltage regulation, that is no feedback (it is the most common case), then most of the time pulse width is maximum - trust the chip making pulses with exactly same length - and changing only at start-up.
Another popular chip is TL494, not much difference in circuitry, operation principles the same.
Anyway, why so much talking and doubts, just try it and enjoy the reality 😀
Normal operation of a transformer should be magnetized and demagnetized periodically. Any unbalanced operation between magnetizing and demagnetizing of a transformer may have the potential of saturation problem. In push-pull operations, the two switch will magnetize and demagnetize the transformer alternately. Operation unbalance can be due to the error of duty cycle of the two switches, the geometrical difference of the two windings connected to the two switches etc. will increase the magnetizing current in one direction period by period and causes saturation. Why many push-pull smps can operate using voltage mode control beacause there are some reasons that will self-balance the mag and demag unbalance. For example, the resistance of the power sw and windings(MOSFET etc). But it can only balance out small unbalance only. The best way is to use peak current mode control (PCMC) which can guarantee safe operation of the transformer and sw. PCMC actually contains two control loops and the output voltage is regulated by controlling the output inductor peak current (sensed from the primary sw). There is absolutely no problem for changing load. For more details, you can visit TI.com find some application notes or SMPS design guidlines.
Wow! So sophisticated theory 🙂
I would say again - there's no practical problem about this.
Well if say in real life slightly non-identical halves in winding/impedance/pulse width etc. make power supply efficiency lowered from 91% to 90% because of this effect who really cares about that 1%.
Certainly unless you've made 4 turns for one half-winding and 5 turns for another
Make primary winding bifilar type - it is the must - and that's it.
There are so many other things to think of beside this...
I would say again - there's no practical problem about this.
Well if say in real life slightly non-identical halves in winding/impedance/pulse width etc. make power supply efficiency lowered from 91% to 90% because of this effect who really cares about that 1%.
Certainly unless you've made 4 turns for one half-winding and 5 turns for another
Make primary winding bifilar type - it is the must - and that's it.
There are so many other things to think of beside this...
Actually, peak current mode control only keeps you from going completely over the cliff into saturation due to flux imbalance. No restoring force is provided by the control to correct any volt-second imbalance, as the current sense loop won't sense any volt second differences until the transformer starts to saturate. You can sort of get around this by gapping the transformer so that the magnetizing current becomes an indicator of transformer volt seconds, but this increases the energy stored in the transformer and also the peak switch current. A good way to solve the problem is to set up the control loop to program volt-seconds using a transformer winding and integrating its output voltage to get the volt-second product for each half cycle. Unequal diode drops, resistive losses and timing differentials will all show up in the volt-seconds. As there isn't any standard control chip around that will do this, you have to jigger one using an external comparator.
To wrenchone: I didn't quite understand the above posts about current mode control in regard to practical issues of that theory (that's maybe because I didn't face such kind of problem ever); but I _DO_ understand the thing of volt-second imbalance in push-pull converter - as it is kind of real life problem.
So I share your thoughts about trying magnetic element volt-second control. But looks like error integrator time constant should be in order of switching cycle - otherwise it looks to be difficult to provide tesla-correction control signal for popular PWM drivers like SG3524/3525 etc. Do you have such experience or any ideas of practical implementation?
So I share your thoughts about trying magnetic element volt-second control. But looks like error integrator time constant should be in order of switching cycle - otherwise it looks to be difficult to provide tesla-correction control signal for popular PWM drivers like SG3524/3525 etc. Do you have such experience or any ideas of practical implementation?
joeliu said:
wrenchone said:
Peak current mode control, or PCMC, should and does provide restoration should the magnetic flux start to staircase. Although the current control loop does not directly sense volt-seconds, which is directly related to magnetic flux density "B", it does sense amperes, which is directly related to magnetic field intensity "H". When "B" shifts due to imbalance, so does "H", and the current loop corrects the asymmetry. The current loop terminates the PWM pulse whenever the sensed current exceeds the control signal from the error amplifier in the voltage control loop. The current does not have to reach a large value, such as that associated with saturation, in order to terminate the pulse. The control loop bandwidth is less than the switching frequency, so that the control signal does not change very much from one pulse to the next. If the load current is only 10% of full load, the pulse will be terminated at that 10% value of current. Should the negative half of the pulse volt-seconds exceed the positive half, since the control signal has hardly changed, the pulse will be terminated just above the 10% current value.
The best way to visualize this action is to draw the B-H loop, then retrace it for non-symmetrical volt-seconds. In addition to "B" walking upward or downward, "H" will attempt to walk leftward or rightward. The current loop terminates this tendency immediately. I have to agree with joeliu on this matter. Best regards.
Well I seem to be confused with current-mode control in push-pull circuit.
I can understand what current mode control means when talking about popular UC3842 single-ended controller - it senses current directly on primary switch. Right now I found newer UC1846 chip at ti.com for push-pull solution. But in circuit example it seem to sense VOLTAGE on SECONDARY side as usual UC1525 does. So what a principal difference?
I remind that in some experiment I made SG3525-based push-pull converter to drive deliberately asymmetrical load - one half-cycle was heavily loaded at about circuit nominal load of 500W while another one was just idling (secondary diode bridge was replaced by a single diode to make half-wave rectification). Result was positive: long time test showed about typical efficiency. Transformer core used was of usual ferrite with permeability of 2000 and I guess that high-mu core doesn't store much energy in magnetic field and transfers almost everything into load. This was an interesting result and I thought that idling half helps to de-gauss core each half cycle. Anyway I'm not completely sure about it till now; can anyone explain this effect?
I can understand what current mode control means when talking about popular UC3842 single-ended controller - it senses current directly on primary switch. Right now I found newer UC1846 chip at ti.com for push-pull solution. But in circuit example it seem to sense VOLTAGE on SECONDARY side as usual UC1525 does. So what a principal difference?
I remind that in some experiment I made SG3525-based push-pull converter to drive deliberately asymmetrical load - one half-cycle was heavily loaded at about circuit nominal load of 500W while another one was just idling (secondary diode bridge was replaced by a single diode to make half-wave rectification). Result was positive: long time test showed about typical efficiency. Transformer core used was of usual ferrite with permeability of 2000 and I guess that high-mu core doesn't store much energy in magnetic field and transfers almost everything into load. This was an interesting result and I thought that idling half helps to de-gauss core each half cycle. Anyway I'm not completely sure about it till now; can anyone explain this effect?
Alme said:Well I seem to be confused with current-mode control in push-pull circuit.
I can understand what current mode control means when talking about popular UC3842 single-ended controller - it senses current directly on primary switch. Right now I found newer UC1846 chip at ti.com for push-pull solution. But in circuit example it seem to sense VOLTAGE on SECONDARY side as usual UC1525 does. So what a principal difference?
I remind that in some experiment I made SG3525-based push-pull converter to drive deliberately asymmetrical load - one half-cycle was heavily loaded at about circuit nominal load of 500W while another one was just idling (secondary diode bridge was replaced by a single diode to make half-wave rectification). Result was positive: long time test showed about typical efficiency. Transformer core used was of usual ferrite with permeability of 2000 and I guess that high-mu core doesn't store much energy in magnetic field and transfers almost everything into load. This was an interesting result and I thought that idling half helps to de-gauss core each half cycle. Anyway I'm not completely sure about it till now; can anyone explain this effect?
Alme, I'm in my 27th year of engineering, and I still learn new stuff with every design. I've designed 6 to 7 dozen SMPS, and I still have much to learn. It took me decades to learn what little I know, and it's hard to explain this subject in a few paragraphs, but here are some short answers to your questions.
With voltage-mode control, VMC, there is but one control loop. Output voltage is sensed and compared to an artificially generated sawtooth waveform, which constitutes natural sampling. When the sawtooth exceeds the control voltage the pulse is terminated. The PWM duty cycle is directly controlled by this method.
With current-mode control, CMC, there are two control loops. The outer loop senses voltage just like VMC, but the amplified error signal, the control voltage, gets compared not to an artificial sawtooth, but a natural sawtooth derived by sensing the inductor current. The inner control loop provides this current waveform. The control voltage directly controls a specific value of inductor current, and the duty cycle is an indirect consequence of inductor current. By controlling inductor current directly, and duty cycle indirectly, sudden changes in load current can be compensated immediately, unlike VMC, where the output must first go out of regulation, so that the error amp can adjust the duty cycle to restore regulation.
Regarding your experiment, having a half wave secondary load is not the same as volt-second unbalance. It is the *magnetizing current* that we must deal with, not the load current. Even when the output rectifier is reverse biased, the primary magnetizing current is still present and resets the core flux each cycle. To simulate a volt-second unbalance, you could insert a resistor in series with the drain on one MOSFET only. This will result in unequal voltage drops for each half pulse, resulting in unbalanced volt seconds.
I've got to run. I hope I've helped. Best regards.
In a nutshell, when you close the loop on the switching power supply, you compare the scaled output of the supply to a reference voltage using an amplifier of some sort. The error signal from this amplifier is applied to the controller to perform any needed corrections in the output voltage.
In a voltage mode supply, the error signal is used to directly program the controller duty cycle .
In a current mode supply, the error signal is used to program the peak current in the switch, which also indirectly affects the duty factor as long as there is some relationship between duty factor and switch current (true, if there is a filter inductor in the output circuit).
Voltage mode leaves the primary switch on for a preset interval, even if a cosmic catastrophe happens in the interim. Current mode can respond to an overload condition or a fault like transformer saturation, and it terminates the switching cycle early. Even though it is not a complete solution for transformer flux walking, current mode at least prevents large fault currents due to hard saturation. Half a loaf, as it were... Engineers usually settle for this, as there are current mode controllers readily available.
I have used a 3842 single ended current mode controller to test the concept of volt-seconds control by feeding an integrated signal from a transformer winding into the current sense pin of the device. As you mentioned, the time constant of the integrator should be such that you sense the volt seconds from each cycle, and you need to reset the integrator every cycle. This could be done using a current mode push pull controller as well. Unitrode/TI makes several suitable controllers, as does Linear Technology. If you Or in a curent sense signal along with the volt-seconds signal, you can retain overcurrent protection. Ordinary voltage mode converters like the 3525 and the TL494 could be used to play this trick, too, but it would require an extra comparator. What you do in that case would be to put a resistor in series with the timing cap and drive it with a positive signal from the comparator. This imposes a voltage step on the timing cap that can be used to terminate a half cycle.
In a voltage mode supply, the error signal is used to directly program the controller duty cycle .
In a current mode supply, the error signal is used to program the peak current in the switch, which also indirectly affects the duty factor as long as there is some relationship between duty factor and switch current (true, if there is a filter inductor in the output circuit).
Voltage mode leaves the primary switch on for a preset interval, even if a cosmic catastrophe happens in the interim. Current mode can respond to an overload condition or a fault like transformer saturation, and it terminates the switching cycle early. Even though it is not a complete solution for transformer flux walking, current mode at least prevents large fault currents due to hard saturation. Half a loaf, as it were... Engineers usually settle for this, as there are current mode controllers readily available.
I have used a 3842 single ended current mode controller to test the concept of volt-seconds control by feeding an integrated signal from a transformer winding into the current sense pin of the device. As you mentioned, the time constant of the integrator should be such that you sense the volt seconds from each cycle, and you need to reset the integrator every cycle. This could be done using a current mode push pull controller as well. Unitrode/TI makes several suitable controllers, as does Linear Technology. If you Or in a curent sense signal along with the volt-seconds signal, you can retain overcurrent protection. Ordinary voltage mode converters like the 3525 and the TL494 could be used to play this trick, too, but it would require an extra comparator. What you do in that case would be to put a resistor in series with the timing cap and drive it with a positive signal from the comparator. This imposes a voltage step on the timing cap that can be used to terminate a half cycle.
Claude and wrenchone, thanks a lot for your explanations.
I suspected the thing about CMC now I'm sure to feel it. Yet UC1846 typical circuit looks incomplete to me because it doesn't directly sense primary current.
And magnetizing current which is part of total primary current is not possible to sense on secondary side, right? and this sensing is more important to my mind.
Seems I've got the right clue about my described experiment, that if half-wave load is applied to center-tap push-pull converter than transformer magnetizing current doesn't change much and still alternates during "idling" half-cycle. Obviuosly high-permeability ferrite cannot accept high magnetizing current without saturation; I think it may be in order of 10% of nominal load current. Now I begin to realize that I merely turned my push-pull converter into classical single-ended forward converter. Everything fits and I feel my head clarified 🙂
I suspected the thing about CMC now I'm sure to feel it. Yet UC1846 typical circuit looks incomplete to me because it doesn't directly sense primary current.
And magnetizing current which is part of total primary current is not possible to sense on secondary side, right? and this sensing is more important to my mind.
Seems I've got the right clue about my described experiment, that if half-wave load is applied to center-tap push-pull converter than transformer magnetizing current doesn't change much and still alternates during "idling" half-cycle. Obviuosly high-permeability ferrite cannot accept high magnetizing current without saturation; I think it may be in order of 10% of nominal load current. Now I begin to realize that I merely turned my push-pull converter into classical single-ended forward converter. Everything fits and I feel my head clarified 🙂
current waveforms
I began to experiment with push-pull dc/dc converters two years ago (12VDC input, obviously from a car ) . Somebody told me that every pwm controller experiment asymmetrical control pulses to switch the mosfets (as Joeliu commented), thus producing a flux unbalance in the core. When I started my tests I didn’t care about it, because I was sure that my controllers doesn’t produced asymmetrical pulses, this way my power output record was set at 200 watts continuous without current waveforms investigated. But five months ago I bought an oscilloscope to work with more patience at my house, so with current sense resistors and the oscilloscope I have found the next behaviour in every design that I have made:
Top trace is the mosfet’s gate-source voltage (only one side of the push-pull arrangement), and the bottom trace is the primary current across the sense resistor, as you can see there is a flux unbalance with no signs of saturation, of course when I ask for more power one of the pulses begin to saturate quickly. For this reason I’m considering to implement current mode control. Adding a gap in the core helps (I have tested it)
So what do you think?
Alme, have you seen this behaviour in your designs? , I´m wondering it
Juan Carlos
I began to experiment with push-pull dc/dc converters two years ago (12VDC input, obviously from a car ) . Somebody told me that every pwm controller experiment asymmetrical control pulses to switch the mosfets (as Joeliu commented), thus producing a flux unbalance in the core. When I started my tests I didn’t care about it, because I was sure that my controllers doesn’t produced asymmetrical pulses, this way my power output record was set at 200 watts continuous without current waveforms investigated. But five months ago I bought an oscilloscope to work with more patience at my house, so with current sense resistors and the oscilloscope I have found the next behaviour in every design that I have made:
An externally hosted image should be here but it was not working when we last tested it.
Top trace is the mosfet’s gate-source voltage (only one side of the push-pull arrangement), and the bottom trace is the primary current across the sense resistor, as you can see there is a flux unbalance with no signs of saturation, of course when I ask for more power one of the pulses begin to saturate quickly. For this reason I’m considering to implement current mode control. Adding a gap in the core helps (I have tested it)
So what do you think?
Alme, have you seen this behaviour in your designs? , I´m wondering it
Juan Carlos
Juan Carlos, I remind that I tried to measure primary current thru transformer center tap a couple of years ago. Indeed I found it slightly asymmetrical, although the difference was not more than in your example. I am used to care in my designs about DC path length symmetry, that is same FET type/quantity, same copper, bifilar primary/secondary winding, rectifier etc. I've seen many SMPS designs made by other guys where copper DC paths were terribly unequal to my mind, but they still operated at about typical efficiency. I begin to care less about pure theory issues as long as it doesn't visibly affect practical operation and practical reliability.
By now, I tend to think that core resets itself during deadtime, otherwise those lots of my converters must have been blown in short time.
Also I dare to say that making transformer core with significantly lower permeability - adding a gap, having another ferrite etc. - may visibly decrease efficiency which is important issue to me. Can you please measure this and approve or disprove this thought.
By the way, let's also consider heating effects. In real life converters always heat under load; practically FET channel on-resistance may become 2 times higher (for 50-60V FET; for higher voltage type even more) than specified in datasheets - they usually put "normalized Rds(on) vs. temperature" in datasheets - and copper/winding DC resistance may become 1,3-1,4 times higher than at room temperature. Only rectifier diodes show lower losses at higher temperature but in general they cannot overcome primary side heating change.
Do you think this effect imply positive or negative feedback on discussed core flux symmetry?
By now, I tend to think that core resets itself during deadtime, otherwise those lots of my converters must have been blown in short time.
Also I dare to say that making transformer core with significantly lower permeability - adding a gap, having another ferrite etc. - may visibly decrease efficiency which is important issue to me. Can you please measure this and approve or disprove this thought.
By the way, let's also consider heating effects. In real life converters always heat under load; practically FET channel on-resistance may become 2 times higher (for 50-60V FET; for higher voltage type even more) than specified in datasheets - they usually put "normalized Rds(on) vs. temperature" in datasheets - and copper/winding DC resistance may become 1,3-1,4 times higher than at room temperature. Only rectifier diodes show lower losses at higher temperature but in general they cannot overcome primary side heating change.
Do you think this effect imply positive or negative feedback on discussed core flux symmetry?
I would like to point out that peak and average current control don't allways solve the flux imbalance problem but they may worsen it instead
I have a full bridge prototype that works fine with voltage control [with series capacitor] but suffers from severe flux imbalance and saturation when using average current control. I've tracked the problem down to a small winding asymetry between secondaries. The control circuit tries to correct this asymetry in order to get symetric current but it has no success, it causes just more flux imbalance
The funniest part is that I need average current control in order to get consistent current sharing and limiting when paralelling several units, so I can't just go back to voltage control
I'm considering placing the buck inductor in the primary side with an additional switch+diode pair and operating the transformer at 100% duty cycle with a balancing capacitor in series. This approach gave me good results in previous prototypes, although I discarded it in favour of secondary-side inductor because of complexity
I have a full bridge prototype that works fine with voltage control [with series capacitor] but suffers from severe flux imbalance and saturation when using average current control. I've tracked the problem down to a small winding asymetry between secondaries. The control circuit tries to correct this asymetry in order to get symetric current but it has no success, it causes just more flux imbalance
The funniest part is that I need average current control in order to get consistent current sharing and limiting when paralelling several units, so I can't just go back to voltage control
I'm considering placing the buck inductor in the primary side with an additional switch+diode pair and operating the transformer at 100% duty cycle with a balancing capacitor in series. This approach gave me good results in previous prototypes, although I discarded it in favour of secondary-side inductor because of complexity
Alme,
I understand that a non-symmetrical dc paths worsen the flux unbalance (btw, is it unbalance or imbalance?, I mean, which word should we use?) , but although you can do it perfectly symmetrical, there can be still an asymmetrical drive pulse problem, and thus, an asymmetrical flux (I think that is the reason why Eva is using full-bridge with series blocking capacitor). And I agree with you about the practical reliability, there are thousands of commercial car audio amplifiers working well with the simplest push-pull approach.
You’ve made me think about the gap vs efficiency, I’ll do the measurements as soon as I can, but please be patient (maybe Eva, or who whishes, can help us here)
About the heat, specially where the supply is regulated and very high currents are involved, I think it will produce a negative feedback because with more resistance, the voltage drop will be higher and to keep the same output power the supply will ask for more current, so the possibility of severe flux imbalance will appear, but again, this is only theory.
Eva, nice to talk with you again!
Is your converter dc-dc or ac-dc?, if it’s dc-dc (12V input) I wonder how big is the series capacitor. Paralleling several units?, what are you doing?, and the last question: have you seen my mails?
I understand that a non-symmetrical dc paths worsen the flux unbalance (btw, is it unbalance or imbalance?, I mean, which word should we use?) , but although you can do it perfectly symmetrical, there can be still an asymmetrical drive pulse problem, and thus, an asymmetrical flux (I think that is the reason why Eva is using full-bridge with series blocking capacitor). And I agree with you about the practical reliability, there are thousands of commercial car audio amplifiers working well with the simplest push-pull approach.
You’ve made me think about the gap vs efficiency, I’ll do the measurements as soon as I can, but please be patient (maybe Eva, or who whishes, can help us here)
About the heat, specially where the supply is regulated and very high currents are involved, I think it will produce a negative feedback because with more resistance, the voltage drop will be higher and to keep the same output power the supply will ask for more current, so the possibility of severe flux imbalance will appear, but again, this is only theory.
Eva, nice to talk with you again!
Is your converter dc-dc or ac-dc?, if it’s dc-dc (12V input) I wonder how big is the series capacitor. Paralleling several units?, what are you doing?, and the last question: have you seen my mails?
To Eva: that's really interesting observation to me!
could you please post the schematic of modified full-bridge with primary inductor? Sorry, I didn't quite catch your idea from verbal description.
To J.Carlos: I'm not sure what is better term to say - unbalance or imbalance - I'm not that good at English 🙂 I hope there's no big difference as long as we understand each other well.
And maybe I didn't express myself well about heating issue. I have tried to imagine this effect like this.
If there is equal DC path for halves but volt-second unbalance due to different drive pulse width or winding turns inequality, then the half with higher volt-second would draw more current and its equivalent serial DC path will increase more because of more heating, thus making its volt-second lower - this is self-regulation effect, or negative feedback to effect.
In case there is equal drive pulses and windings but different DC paths (weak connection, or narrow copper at one side, different FET channels, etc.) then there may be either self-regulation or self-deregulation, depending on difference in DC path (significant difference will rather deregulate effect).
This looks like it was already stated above: if volt-second unbalance is slight then it can regulate itself by some means, obviously including additional heating.
could you please post the schematic of modified full-bridge with primary inductor? Sorry, I didn't quite catch your idea from verbal description.
To J.Carlos: I'm not sure what is better term to say - unbalance or imbalance - I'm not that good at English 🙂 I hope there's no big difference as long as we understand each other well.
And maybe I didn't express myself well about heating issue. I have tried to imagine this effect like this.
If there is equal DC path for halves but volt-second unbalance due to different drive pulse width or winding turns inequality, then the half with higher volt-second would draw more current and its equivalent serial DC path will increase more because of more heating, thus making its volt-second lower - this is self-regulation effect, or negative feedback to effect.
In case there is equal drive pulses and windings but different DC paths (weak connection, or narrow copper at one side, different FET channels, etc.) then there may be either self-regulation or self-deregulation, depending on difference in DC path (significant difference will rather deregulate effect).
This looks like it was already stated above: if volt-second unbalance is slight then it can regulate itself by some means, obviously including additional heating.