Hi,
Firstly, I’d like to thank everyone for their input – much appreciated – I’m very grateful.
I’ve had a few days away from the amps and in this time I sent the MOSFETs back to Profusion for testing on a Curve Tracer. Profusion claim there is nothing wrong with them.
Although it’s odd that I can swap the VAS around, with one bank of 4 x N + 4 x P MOSFETs working fine and the other 8 x N + 8 x P not working in any combination, regardless of VGS matching, at this point I can only suspect that my layout is at fault...
I’m not convinced this is an oscillation btw. The Zobel resistor (carbon-film) is not getting hot, nor is there a fuzzy trace on my ‘scope (it’s only 20 Meg, so I assume oscillation at a higher frequency will give a blurred trace).
If I connect a dummy load, the amp isn’t happy at all and draws plenty of current. To reiterate, with the bad amp, the linearity of the bias trimmer is very odd; it’s not progressive. The bias current jumps from 150ma to 1A in a flash, in contrast to the working amp.
The bad amp seems to work up to +/- 9v from the bench supply, giving a healthy-looking Sine / Square, but when you up the voltage it collapses and a massive DC offset appears at output.
I have 2 questions:
Rod Elliot’s design (as well as many others) uses low-value non-inductive Source resistors. However, Profusion suggest mounting the MOSFETs on a transfer bracket, with the Sources connected through the bracket for minimal inductance… If I do this, I can’t use Source resistors… Who’s right, Rod + other designers, or Profusion?
Profusion link: http://www.profusionplc.com/static/images/data sheets/apnotes.pdf
Secondly, if you’ve run out of PCB space for MOSFETs, how would you common them? I assume it’d be risky to common the Gate resistor returns (resistor mounted at MOSFET pin) back to the PCB and the Source back to the PCB via a thick 45A solid wire? It’d be better to go for a ‘STAR’ arrangement, where Gate and Source for each device meet at a high-quality point on the PCB, similar to a PSU Star Ground. How about I weld a thick bar to the PCB for the Gate and Source, and connect each device via solder tags? If I use 30A multi-strand cable, will its inductance be an issue?
What say you?
Many thanks again,
Justin
Firstly, I’d like to thank everyone for their input – much appreciated – I’m very grateful.
I’ve had a few days away from the amps and in this time I sent the MOSFETs back to Profusion for testing on a Curve Tracer. Profusion claim there is nothing wrong with them.
Although it’s odd that I can swap the VAS around, with one bank of 4 x N + 4 x P MOSFETs working fine and the other 8 x N + 8 x P not working in any combination, regardless of VGS matching, at this point I can only suspect that my layout is at fault...
I’m not convinced this is an oscillation btw. The Zobel resistor (carbon-film) is not getting hot, nor is there a fuzzy trace on my ‘scope (it’s only 20 Meg, so I assume oscillation at a higher frequency will give a blurred trace).
If I connect a dummy load, the amp isn’t happy at all and draws plenty of current. To reiterate, with the bad amp, the linearity of the bias trimmer is very odd; it’s not progressive. The bias current jumps from 150ma to 1A in a flash, in contrast to the working amp.
The bad amp seems to work up to +/- 9v from the bench supply, giving a healthy-looking Sine / Square, but when you up the voltage it collapses and a massive DC offset appears at output.
I have 2 questions:
Rod Elliot’s design (as well as many others) uses low-value non-inductive Source resistors. However, Profusion suggest mounting the MOSFETs on a transfer bracket, with the Sources connected through the bracket for minimal inductance… If I do this, I can’t use Source resistors… Who’s right, Rod + other designers, or Profusion?
Profusion link: http://www.profusionplc.com/static/images/data sheets/apnotes.pdf
Secondly, if you’ve run out of PCB space for MOSFETs, how would you common them? I assume it’d be risky to common the Gate resistor returns (resistor mounted at MOSFET pin) back to the PCB and the Source back to the PCB via a thick 45A solid wire? It’d be better to go for a ‘STAR’ arrangement, where Gate and Source for each device meet at a high-quality point on the PCB, similar to a PSU Star Ground. How about I weld a thick bar to the PCB for the Gate and Source, and connect each device via solder tags? If I use 30A multi-strand cable, will its inductance be an issue?
What say you?
Many thanks again,
Justin
the 2sk2221 and 2sj352 are much more stable than the 2sk1058 and 2sj162 and 8amp the problem being the 1058
aandy
aandy
aandy said:
That's what I have always thought: negative thermal characteristic
Why do designs such as Elliot's implement lateral devices with Source resistors?
J
there rds on goes up with increased temprature unlike a bipolar.
that current hog!
no source resister needed.
stability is King to mosfet amplifiers all of them.
pcb layout is the LAW to fet amps.
and you need a good old analog scope.
didgital scopes are close to usles and my hp is 100mhz
andy
ps and a scelpal to cut the copper
that current hog!
no source resister needed.
stability is King to mosfet amplifiers all of them.
pcb layout is the LAW to fet amps.
and you need a good old analog scope.
didgital scopes are close to usles and my hp is 100mhz
andy
ps and a scelpal to cut the copper
I can remember reading in the dim and distant past that lateral mosfets had a negative characteristic up to a point! but at about 100ma this slowley changed to a posative !!!
Beside of which a low value resistor is of great convenience when you want to compare the standing current in each device to check for current hogging .
As to Gate resistors they have always been used and put as close as posssibe to the output devices
Supply decoupling I have always assumed this would have been done ditto the zobel network
I have built many amps and have always got them stable in the end
regards Trev
Beside of which a low value resistor is of great convenience when you want to compare the standing current in each device to check for current hogging .
As to Gate resistors they have always been used and put as close as posssibe to the output devices
Supply decoupling I have always assumed this would have been done ditto the zobel network
I have built many amps and have always got them stable in the end
regards Trev
i never test the fets at that low current.
10 watts of disapation at a 100volt rails would heat the fet up.
if you know what the scope trace means then getting them working is no problem.
i have seen batches of fets with inherent stability problems.
both with semilab and hitatchi.
over the years.
my bigest amp has 32 pairs in it
andy
10 watts of disapation at a 100volt rails would heat the fet up.
if you know what the scope trace means then getting them working is no problem.
i have seen batches of fets with inherent stability problems.
both with semilab and hitatchi.
over the years.
my bigest amp has 32 pairs in it
andy
All MOSFETs have an inflection in the gm vs temperature graph. Lateral MOSFETs have this at about 20mA per A of Idmax. So, Renesas/Hitachi 7A devices will exhibit about zero Tc at around 100-150mA. Semelab will be slightly higher because they have higher Idmax - the reason for this is simple, the MOSFETs themselves are constructed as arrays of cells in parallel - BUZ types, being 8A (IIRC) are a bit larger. It is a nice convenience that this current is very close to what could be considered optimum bias for these MOSFETs (*)
Vertical MOSFETs (including PI-MOS process of the Toshiba audio MOSFETs) have this point of inflection at a MUCH higher current, often close to the Idmax, so these need to be compensated thermally. The position of the point of inflexion is ependent on the technology, but in general technology that produces higher gm in a MOSFET also moves this point further up in current.
(*) BJT output stages in common collector tend to exhibit an optimum bias point, with the least distortion. MOSFETs do not have an equivalent to this, and in general operate the better the higher the bias, but after a certain pont (about 100-200mA per pair) the law of diminishing returns steps in and you don't get nearly as much improvement as you do produce extra heat.
Regarding paralleling MOSFETs, with laterals, source resistors are not needed if a modest amount of selection based on treshold voltage is done. Source resistors in MOSFET amps in general can be a problem because the 'usual' part to use there is wirewound. One of the reasons MOSFETs socillate is inductance in the source line - even that of the source lead - so you really don't want to add to it. With lateral MOSFETs, there is another consideration - the source resistors lower the already very low gm of the part. It is a matter of very careful consideration wether addition of source resistors on lateral MOS produces lower THD - it can equaly as easily produce higher THD, requiring additional swing from the driver stage due to reduced gm.
With vertical and like constructions (Toshiba), the high gm (easily 10x that of a lateral MOSFET) demands source resistors when these parts are paralleled. Although their gm is higher than that of laterals, it is still low compared to BJTs, so lower valued source resistors are preferred. Unfortunately, tolerances in Vth and gm require much higher source resistors than would be typically found in BJT output amps. Doing a moderate amount of selection of the MOSFETs based on treshold voltage can relax this condition, and quite low source resistors can then be used (0.1 ohm).
In contrast, the gm of BJTs is so high that their tolerances normally prevent usage in follower PP stages without some kind of emitter resistance, even if only a single pair is used (**). This is not so with MOSFETs, their lower gm and in some cases (HEXFET) higher Vth alowes use without source resistors when a single pair is used. The use of source resistors may only become necessary when paralleling pairs.
(**) There are exceptions to this rule. Although it is not apparent, some power BJT technologies in use today actually produce a distributed emitter resistor within the transistor itself. Most modern audio power BJTs are of this kind - they are known as LAPT, tripple diffused, RET, etc. In these constructions, variations of the cell based structure are used, where many smaller BJT structures are in parallel, with their own integrated emitter resistor.
Amongst others, Doug Self has shown that for the EF output topology the optimum bias point is expressed as the voltage across the external emitter resistor, which tends to stay constant. The clue that you are dealing with a transistor technology that uses some sort of internal emitter resistance is when the optimum bias current is much lower than Self's data oredicts (usually by about 50%). This indicates that the actual equivalent emitter resistance is larger than the external part, meaning there is more of it inside the transistor itself. This fact makes it possible to use these transistors without external emitter resistors, if the thermal coupling of the bias servo is very high - hence the introduction of parts with integrated temperature sensing diodes.
Vertical MOSFETs (including PI-MOS process of the Toshiba audio MOSFETs) have this point of inflection at a MUCH higher current, often close to the Idmax, so these need to be compensated thermally. The position of the point of inflexion is ependent on the technology, but in general technology that produces higher gm in a MOSFET also moves this point further up in current.
(*) BJT output stages in common collector tend to exhibit an optimum bias point, with the least distortion. MOSFETs do not have an equivalent to this, and in general operate the better the higher the bias, but after a certain pont (about 100-200mA per pair) the law of diminishing returns steps in and you don't get nearly as much improvement as you do produce extra heat.
Regarding paralleling MOSFETs, with laterals, source resistors are not needed if a modest amount of selection based on treshold voltage is done. Source resistors in MOSFET amps in general can be a problem because the 'usual' part to use there is wirewound. One of the reasons MOSFETs socillate is inductance in the source line - even that of the source lead - so you really don't want to add to it. With lateral MOSFETs, there is another consideration - the source resistors lower the already very low gm of the part. It is a matter of very careful consideration wether addition of source resistors on lateral MOS produces lower THD - it can equaly as easily produce higher THD, requiring additional swing from the driver stage due to reduced gm.
With vertical and like constructions (Toshiba), the high gm (easily 10x that of a lateral MOSFET) demands source resistors when these parts are paralleled. Although their gm is higher than that of laterals, it is still low compared to BJTs, so lower valued source resistors are preferred. Unfortunately, tolerances in Vth and gm require much higher source resistors than would be typically found in BJT output amps. Doing a moderate amount of selection of the MOSFETs based on treshold voltage can relax this condition, and quite low source resistors can then be used (0.1 ohm).
In contrast, the gm of BJTs is so high that their tolerances normally prevent usage in follower PP stages without some kind of emitter resistance, even if only a single pair is used (**). This is not so with MOSFETs, their lower gm and in some cases (HEXFET) higher Vth alowes use without source resistors when a single pair is used. The use of source resistors may only become necessary when paralleling pairs.
(**) There are exceptions to this rule. Although it is not apparent, some power BJT technologies in use today actually produce a distributed emitter resistor within the transistor itself. Most modern audio power BJTs are of this kind - they are known as LAPT, tripple diffused, RET, etc. In these constructions, variations of the cell based structure are used, where many smaller BJT structures are in parallel, with their own integrated emitter resistor.
Amongst others, Doug Self has shown that for the EF output topology the optimum bias point is expressed as the voltage across the external emitter resistor, which tends to stay constant. The clue that you are dealing with a transistor technology that uses some sort of internal emitter resistance is when the optimum bias current is much lower than Self's data oredicts (usually by about 50%). This indicates that the actual equivalent emitter resistance is larger than the external part, meaning there is more of it inside the transistor itself. This fact makes it possible to use these transistors without external emitter resistors, if the thermal coupling of the bias servo is very high - hence the introduction of parts with integrated temperature sensing diodes.
Hi,
Firstly, I’d like to thank everyone again for helping out – much appreciated!
Before I take the casework to the machinist, I’d like to ask the group if they think this plan is ok:
Each amp is a mono-block.
Each MOSFET will have a 220pF cap between Source and Gate
Each MOSFET will have a 100v / 220u low-ESR cap between Drain and Source
The 4 x N-Channel MOSFETS will be mounted on an L-Bracket, with their Sources connected through the alloy bracket
The 4 x P-channel MOSFETS will be the same, but on another bracket.
The Gate and Drain wiring will be in a ‘Star’ configuration – a bit like a HQ ground point.
I intend to weld a thick solid bar from the PCB to each L-Bracket to minimise any inductance, as per-Profusion’s apps data.
My question is this:
In the enclosure I have, the heatsinks will be 210mm apart… That means the N-channel bank will be approximately 190mm away from the P-channel bank, with the PCB in the middle… Will this be a problem? Is it ok to run the N-channel down one side, and the P–channel down the other, with so much distance between them?
Many thanks in advance for any comments.
Justin
Firstly, I’d like to thank everyone again for helping out – much appreciated!
Before I take the casework to the machinist, I’d like to ask the group if they think this plan is ok:
Each amp is a mono-block.
Each MOSFET will have a 220pF cap between Source and Gate
Each MOSFET will have a 100v / 220u low-ESR cap between Drain and Source
The 4 x N-Channel MOSFETS will be mounted on an L-Bracket, with their Sources connected through the alloy bracket
The 4 x P-channel MOSFETS will be the same, but on another bracket.
The Gate and Drain wiring will be in a ‘Star’ configuration – a bit like a HQ ground point.
I intend to weld a thick solid bar from the PCB to each L-Bracket to minimise any inductance, as per-Profusion’s apps data.
My question is this:
In the enclosure I have, the heatsinks will be 210mm apart… That means the N-channel bank will be approximately 190mm away from the P-channel bank, with the PCB in the middle… Will this be a problem? Is it ok to run the N-channel down one side, and the P–channel down the other, with so much distance between them?
Many thanks in advance for any comments.
Justin
hi Justin,
the 100V/220u low ESR cap between drain and source, did you mean drain and ground?
if so i would bypass them with 100n as well.
with regard to the Mos fet's being bolted to the L brackets and commoning the sources through them. i have had instability problems with this method, i found insulating the fets from the bracket, and firmly grounding the brackets to be much more stable method.
also if they are commoned in this way how will you insulate the L bracket/heatsink from ground?
as regard to layout, the mosfet's wiring neeeds to be keeped as short as possible, point to point is best. the disance you propose seems too long to me (100mm each bank)
something to consider also is rather than parallel extra devices in this way you could try the 'dual die Mos' Fet's these are efectivly two paralleled devicies in one can BUZ900D.
regards
bob
the 100V/220u low ESR cap between drain and source, did you mean drain and ground?
if so i would bypass them with 100n as well.
with regard to the Mos fet's being bolted to the L brackets and commoning the sources through them. i have had instability problems with this method, i found insulating the fets from the bracket, and firmly grounding the brackets to be much more stable method.
also if they are commoned in this way how will you insulate the L bracket/heatsink from ground?
as regard to layout, the mosfet's wiring neeeds to be keeped as short as possible, point to point is best. the disance you propose seems too long to me (100mm each bank)
something to consider also is rather than parallel extra devices in this way you could try the 'dual die Mos' Fet's these are efectivly two paralleled devicies in one can BUZ900D.
regards
bob
I hope you can fix your problem.
Maybe you need to break th e problem down so that you can start to look in the right place
1. Please post th circuit with the measured voltages on the good amp cct vs the bad amp
2. Is your problem in fact oscillation - not a hiarline crack on the board or even on a resistor (yeah, I've had that one before)
3. If it really is oscillation then: is it loop stability oscillation (500kHz to probably no more than 2MHz) or is it parasitics in the output stage (>>2MHz). I don't understand why your Zobel is not frying if your amp is oscillating, or why the output stage is not getting hot.
Good suggestion by Andrew about interposing a buffer stage between the VAS and the mosfets. However, I have to say the simplicity of the design as per your post is its attractiveness.
Maybe you need to break th e problem down so that you can start to look in the right place
1. Please post th circuit with the measured voltages on the good amp cct vs the bad amp
2. Is your problem in fact oscillation - not a hiarline crack on the board or even on a resistor (yeah, I've had that one before)
3. If it really is oscillation then: is it loop stability oscillation (500kHz to probably no more than 2MHz) or is it parasitics in the output stage (>>2MHz). I don't understand why your Zobel is not frying if your amp is oscillating, or why the output stage is not getting hot.
Good suggestion by Andrew about interposing a buffer stage between the VAS and the mosfets. However, I have to say the simplicity of the design as per your post is its attractiveness.
Hi,
I did mean Drain and Ground!
This whole situation has been a nightmare.... To have one amp working fine, but not be able to get another working, even with the same VAS is beyond annoying.
Bonsai - I don't think it's oscillation. I see no 'blur' on my 'scope and the Zobel isn't hot. If it's not oscillation, what would cause such a massive negative offset at the output?
I really don't know what to do now. I've never had anything this frustrating in my life. I really wish I'd just bought a commercial amp instead of trying to parallel my original amp's output FETs.
The original arrangement cost me £165 in metalwork fees ($300 USD); if the new arrangement doesn't work, that'll be another £100+ down the toilet.
Thanks again,
Justin
I did mean Drain and Ground!
This whole situation has been a nightmare.... To have one amp working fine, but not be able to get another working, even with the same VAS is beyond annoying.
Bonsai - I don't think it's oscillation. I see no 'blur' on my 'scope and the Zobel isn't hot. If it's not oscillation, what would cause such a massive negative offset at the output?
I really don't know what to do now. I've never had anything this frustrating in my life. I really wish I'd just bought a commercial amp instead of trying to parallel my original amp's output FETs.
The original arrangement cost me £165 in metalwork fees ($300 USD); if the new arrangement doesn't work, that'll be another £100+ down the toilet.
Thanks again,
Justin
> i would bypass them with 100n as well.
Will a ceramic cap be ok for this? I have some in a tray.
> also if they are commoned in this way how will you insulate the L bracket/heatsink from ground?
I was going to buy a strip of silicon rubber compound (the same as the semiconductor mounting strip) and cut it to size – you can get it from Farnell
> something to consider also is rather than parallel extra devices in this way you could try the 'dual die Mos' Fet's these are efectivly two paralleled devicies in one can BUZ900D.
I’ve spent £200 on MOSFETs. I can’t sell them as they’ve been soldered to. They have been tested by Profusion. I like the sound of Lateral MOSFETs as well.
> Please post th circuit with the measured voltages on the good amp cct vs the bad amp
The good amp was taken apart so that the MOSFETs could be tested on a Curve Tracer. Now that it’s in so many pieces, it will be difficult to reassemble – I was planning to make an all-new layout…
Thanks,
J
Will a ceramic cap be ok for this? I have some in a tray.
> also if they are commoned in this way how will you insulate the L bracket/heatsink from ground?
I was going to buy a strip of silicon rubber compound (the same as the semiconductor mounting strip) and cut it to size – you can get it from Farnell
> something to consider also is rather than parallel extra devices in this way you could try the 'dual die Mos' Fet's these are efectivly two paralleled devicies in one can BUZ900D.
I’ve spent £200 on MOSFETs. I can’t sell them as they’ve been soldered to. They have been tested by Profusion. I like the sound of Lateral MOSFETs as well.
> Please post th circuit with the measured voltages on the good amp cct vs the bad amp
The good amp was taken apart so that the MOSFETs could be tested on a Curve Tracer. Now that it’s in so many pieces, it will be difficult to reassemble – I was planning to make an all-new layout…
Thanks,
J
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