Hi !
Has anyone worked with ES9023 DAC ? I want to build one for myself and I have a few questions about it.
https://www.mouser.com/datasheet/2/1082/ES9023_Datasheet_v0_72-3074267.pdf
Can I send the audio data with an ESP32 over I2S ? The main problem is that I don't know what should I do with the MCLK pin. As far as I understand, it is said that this DAC can work in 2 modes: Asynchronous and Synchronous. But there is no information on how to implement this. I asked the AI and it says that in Synchronous mode the DAC can generate a master clock form the I2S clock signals. Is this true ? If this is possible, what should I do with the MCLK pin from the DAC ? I let it floating ?
Has anyone worked with ES9023 DAC ? I want to build one for myself and I have a few questions about it.
https://www.mouser.com/datasheet/2/1082/ES9023_Datasheet_v0_72-3074267.pdf
Can I send the audio data with an ESP32 over I2S ? The main problem is that I don't know what should I do with the MCLK pin. As far as I understand, it is said that this DAC can work in 2 modes: Asynchronous and Synchronous. But there is no information on how to implement this. I asked the AI and it says that in Synchronous mode the DAC can generate a master clock form the I2S clock signals. Is this true ? If this is possible, what should I do with the MCLK pin from the DAC ? I let it floating ?
To build with ESS dac chips, first you have to understand how to read their datasheets.
Digital settings in I2C bus registers are notated in bit-literal format (something historically more often seen with FPGAs). If you don't know how to read them or how to program a dac using I2C bus, then its an additional step that might be worth learning. If interested, I would be happy to point you to some posts on the subject.
Regarding MCLK, that is the master clock that clocks the dac output. For best results it should come from a crystal clock module rated appropriately for dac use. Also the crystal clock should run on very clean power. The other thing that should have especially clean power with most or all ESS dac chips are the AVCC inputs, AVCC_L and AVCC_R
Digital settings in I2C bus registers are notated in bit-literal format (something historically more often seen with FPGAs). If you don't know how to read them or how to program a dac using I2C bus, then its an additional step that might be worth learning. If interested, I would be happy to point you to some posts on the subject.
Regarding MCLK, that is the master clock that clocks the dac output. For best results it should come from a crystal clock module rated appropriately for dac use. Also the crystal clock should run on very clean power. The other thing that should have especially clean power with most or all ESS dac chips are the AVCC inputs, AVCC_L and AVCC_R
@jean-paul, Here they use a dedicated MCLK signal. But I was curious if I can use it in synchronous mode (with clock derived from I2S clock).
@Markw4, I know how to use I2C, but this chip doesn't have an I2C interface.
@Markw4, I know how to use I2C, but this chip doesn't have an I2C interface.
@Sigismund : IMO your AI response is typical AI hallucination - it merges information from several DACs. AFAIK ESS DACs cannot generate master clock (MCLK) from the incoming I2S bitclock. Unlike e.g. TI DACs like PCM5102 or PCM5242 which do have a PLL for that.
Synchronous mode in ESS parlance means the chip disables asynchronous resampling of incoming I2S to MCLK pace and expects the MCLK to be at fixed multiple of (i.e. synchronous with) fs/bclk - see table MCLK on page 4 of ES9023 datasheet. IMO MCLK pin must always be fed some MCLK signal. If synchronous with I2S at a supported multiple - use synchronous mode, if asynchronous (typically a separate crystal/clock) - use asynchronous mode with ASRC enabled.
IIUC ESP32 does provide MCLK used by its I2S interface, as described in https://docs.espressif.com/projects/esp-idf/en/stable/esp32/api-reference/peripherals/i2s.html . This thread seems to configure the MCLK output pin https://esp32.com/viewtopic.php?t=14185 .
Synchronous mode in ESS parlance means the chip disables asynchronous resampling of incoming I2S to MCLK pace and expects the MCLK to be at fixed multiple of (i.e. synchronous with) fs/bclk - see table MCLK on page 4 of ES9023 datasheet. IMO MCLK pin must always be fed some MCLK signal. If synchronous with I2S at a supported multiple - use synchronous mode, if asynchronous (typically a separate crystal/clock) - use asynchronous mode with ASRC enabled.
IIUC ESP32 does provide MCLK used by its I2S interface, as described in https://docs.espressif.com/projects/esp-idf/en/stable/esp32/api-reference/peripherals/i2s.html . This thread seems to configure the MCLK output pin https://esp32.com/viewtopic.php?t=14185 .
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@phofman
Ok, I will use a crystal oscillator on MCLK pin. I think it's cleaner than the one generated by ESP32 and I also get rid of its configuration (as I am verry new to ESP32).
I selected this one: https://www.lcsc.com/datasheet/lcsc...ators-OT1EL89CJI-111YLC-12-288M_C41415699.pdf
Will it be good enough for audio ?
Its specs are:
- Frequency: 12.288 MHz (256xFs, Fs = 48KHz)
- Supply voltage: 1.8-3.3V
- Supply current: 5mA @3.3V
- Freq. tolerance: +/- 20ppm
- Temperature stability: +/- 10ppm
- Output load: 15pF
- Rise/fall time: 4ns
- Phase jitter: 0.7ps
In this case, if I use synchronous mode, with dedicated oscillator on MCLK pin with frequency 256 x Fs, how can I tell the ESS chip which mode I want to use ? It doesn't have any software configuration interface (I2C), nor hardware configuration pins for that. Can the chip automatically detect the configuration ?
Ok, I will use a crystal oscillator on MCLK pin. I think it's cleaner than the one generated by ESP32 and I also get rid of its configuration (as I am verry new to ESP32).
I selected this one: https://www.lcsc.com/datasheet/lcsc...ators-OT1EL89CJI-111YLC-12-288M_C41415699.pdf
Will it be good enough for audio ?
Its specs are:
- Frequency: 12.288 MHz (256xFs, Fs = 48KHz)
- Supply voltage: 1.8-3.3V
- Supply current: 5mA @3.3V
- Freq. tolerance: +/- 20ppm
- Temperature stability: +/- 10ppm
- Output load: 15pF
- Rise/fall time: 4ns
- Phase jitter: 0.7ps
In this case, if I use synchronous mode, with dedicated oscillator on MCLK pin with frequency 256 x Fs, how can I tell the ESS chip which mode I want to use ? It doesn't have any software configuration interface (I2C), nor hardware configuration pins for that. Can the chip automatically detect the configuration ?
For asynchronous just use a 50 MHz good one. Not a crystal but a 3.3V XO with its own regulator. Make sure to feed ES9023 3.6V. With today's knowledge I would pick TPS7A2033 and TPS7A2036 for that as they are both cheap and good. You can reinvent the wheel or have a look how other ES9023 designs are designed. The negative voltage situation (charge pump) deserves extra care as it is determining the final result more than other things. No knowledge of ESP32 and such.
It helps to read the full data sheet, it is a simple but well performing IC.
It helps to read the full data sheet, it is a simple but well performing IC.
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@jean-paul
Why 50MHz ? It shouldn't be a multiple of sampling frequency ?
And beside that, higher freqency needs a more carefull PCB design (I'm not verry good at RF).
My ES9023 will be powered from 3.3V, not 3.6V, because I don't need 2Vrms output. In fact, those 1.9Vrms (at 3.3V) are way to much for what I need. I need about 0.5Vrms input im my amplifier for full power output.
Why 50MHz ? It shouldn't be a multiple of sampling frequency ?
And beside that, higher freqency needs a more carefull PCB design (I'm not verry good at RF).
My ES9023 will be powered from 3.3V, not 3.6V, because I don't need 2Vrms output. In fact, those 1.9Vrms (at 3.3V) are way to much for what I need. I need about 0.5Vrms input im my amplifier for full power output.
According to datasheet there is no way to configure ASYNC or SYNC mode, just put any MCLK and it will be in ASYNC. You will use it with only one fixed fs ? If you don't need 96/192K then put any clock >10Mhz. I recommend KC3225K12, it is cheap and has good phase noise specs.
If your MCLK is not synchronous with the I2S signal, the asynchronous resampler enabled by the async mode must resample between the incoming clock and the MCLK clock (they are never exact multiple, every clock runs at a slightly different pace).
Now the question is how the chip detects that MCLK is asynchronous. IMO the only way for a fast detection is measuring whether it's the supported multiple - then synchronous. A quick measurement cannot reveal that MCLK is actually asynchronous (the frequencies would differ only by a tiny bit), and the chip can switch to synchronous instead, resulting in dropouts in the long run. I would use a frequency somewhere between the multiples, just to make sure this may not happen.
Yes I use the same approach.
The only problem with (regular) ESP32 WROOM is that MCLK signal can be connected only to GPIO0.
@phofman and @Anatolii_A
Ok then, It makes sense. I will use a XO that is not Fs multiple, to force the DAC in asynchronous mode. But the audio quality will still be good enough ?
Now, with an asynchronous MCLK, can I use any Fs I want (as long it is 192x lower that my XO MCLK ?
Ok then, It makes sense. I will use a XO that is not Fs multiple, to force the DAC in asynchronous mode. But the audio quality will still be good enough ?
Now, with an asynchronous MCLK, can I use any Fs I want (as long it is 192x lower that my XO MCLK ?
If ESP32 allows external MCLK for its I2S interface (decent implementations of I2S interface allow it), another option would be generating MCLK and using it for the DAC and slaved I2S interface in ESP32. That would avoid the async resampling too. But I do not know if it's possible with ESP32.
Those 50MHz as suggested above is a rather standard frequency for ESS chips. Also 50MHz in https://www.diyaudio.com/community/threads/es9023-dac-usb-asynchronous-input-tas1020b.231049/
Is there any advantage of external XO instead of MCLK generated by ESP32?
I tested both options, but finally used synchronous mode.
I tested both options, but finally used synchronous mode.
Higher frequency - more phase noise, if it will not play 192K it is more profitable to put here lower freq oscillator.