Likewise, reducing the current in J2 and J4 with source resistors also degraded the performance.
Dave
In what way did it degrade performance. THis is interesting to me since most jfet documents suggest that it is best to run jfet current sources at about 40-50% of Idss.
Yes, theoretically; although, if you don't double the IDSS of the device in order to do so, then you end up with 1/2 raw bias on the physical device; thus degraded performance.
To run the sink at 40/50% of its IDSS, then better use a V grade in order to do so
I think it can achieve more precise current flow with source resistor and @ 50% IDSS, because of reduced thermal runaway Best,
nAr
why?
can you link us to an example showing better CCS performance @~50% of Idss?
I would much prefer to ensure sufficient voltage to maintain good current control which I think is made worse by adding a source resistor.
i.e. a 5mA jFET operating at 5Vds to 10Vds is better than 10mA + source resistor when fed at 5Vdg to 10Vdg is my understanding. Am I wrong?
I will try to find the notes that speak about using lower Idss. I believe the reason for doing so has to do with "mitigating temperature variation" as I remember. Don't quote me. I clearly don't know much, just trying to figure it all out.
http://www.tkhifi.com/div/Erno_Borbely_fet_articel_1.pdf
I don't know if this explains what i am thinking or i have misread it(very possible)
Pg.27 - bottom of second paragraph into third.
All,
My apologies for the late reply. I am leaving shortly and will be unavailable for a few days.
The distortion went up appreciably at higher gains. The input pair are also the sole gain devices and output drivers. They have to drive the feedback network and whatever load exsists on the output. They seem to like more current. Try the simulations and see how it reacts. I plan to do some further testing this month with it.
Dave
My apologies for the late reply. I am leaving shortly and will be unavailable for a few days.
The distortion went up appreciably at higher gains. The input pair are also the sole gain devices and output drivers. They have to drive the feedback network and whatever load exsists on the output. They seem to like more current. Try the simulations and see how it reacts. I plan to do some further testing this month with it.
Dave
It would make sense that if the Idss was dropped that the gain would be affected at higher levels. Is it true that in lowering Idss, you are restablishing the level of relative gain and pushing to far beyond this will cause the distortion you are speaking of. I am saying all this with limited understanding based on genreal articles and concepts like Nelon Pass' article - "The Sweet Spot". you all have much greater knowlege of what is going on and I am only trying to understand. I would imagine, Dave, that you are in the very process of trying to find the sweet spot. Did you happen to read the boberly article. I find it interesting that he uses two different Jfets choosing each for its specific characteristics. Perhaps this would not work in your topology. This is where my lack of understanding caomes in. I am trying this with LTSpice, but this is the first time I have used the program.
I agree with Andrew about simply using a lower Idss device run at saturation as a current source. Much more stable.
As I don't really understand the operation of this circuit yet, the proof will be in the pudding. As I see it, it operates into the forward bias region, and that doesn't fit well in my little pea brain.
As I don't really understand the operation of this circuit yet, the proof will be in the pudding. As I see it, it operates into the forward bias region, and that doesn't fit well in my little pea brain.
Yes, all gain devices like to have more idle current
As you say the diff. pair has to drive the feedback network + load. This affects the gain you can get out of the circuit, but hey ! No other way
I would try to reference gates to GND by 100k, suppress R5, R8 & R9, and try to find a different biasing scheme for the J2/J4; e.g. higher IDSS grade with a source resistor ( 0,3V at given current). I don't think dynamically bias the CS helps the operation on a line stage
I don't think IDSS for a jfet CS gives a very stable current out of the device, because the body temperature of the TO92 is also important trouble factor. At IDSS it is likely to be disturbed by body case, and then it is more sensitive to external air temperature changes (or even transmitted by the board). That is also why in B1 cases the output offset is more stable by thermally coupling the devices, it helps to get rid of the little thermal runaways. The case where we don't matter it fluctuates a little is when we bias one very well matched diff. pair with only one jfet at IDSS as current source. That could be done using a V grade or at least 2 times the IDSS of each of the diff. pair.
But in fact, I saw a funny thing on my milli-ampmeter while matching jfets by IDSS, using the well known self biasing scheme. I had a GR lot to be done, then a BL. I could see the following behaviour: the lowest IDSS GRs had a quicker and more stable IDSS reading than the BL ones, even between the BLs, the ones having the higher IDSS were very long to get stable value readings ! I think as the current flow grows, the thermal case of the TO92 acts more and more and device is slightly hotter too; this is a problem we would like to see removed
either by design, either using adequate heatsinking, e.g. thermal coupling I don't think so, as otherwise the diff. pair couldn't get the swing amplified
Brds,
nAr
This is the part of the scheme I am not understanding. All other schems have a gate resistor connecting to ground and biasing the gate negative in relation to drain and this limits Id and establishes bias point. IN the scheme it seems the Jfets are biased at sauration. If J2 is sinking 10mA, that means R1 is dropping 15V. That leaves +5V plus -20V which sums to -15V and is equally divided by R4 and R5. This leaves the gate of -7.5V. The source is also sitting at -7.5V, and these sum to 0v potential. At 0V, the current is passing at Idss which is 10mA, so when any positive voltage is applied to the gate of J1, it is forward biased. Normally, the Jfet would increase current as an attempt to equalize, this would drop current across R1 decrerasing voltage drop, and creating an inverted response to the signal. If this happens quickly, then all is fine, otherwise you jeapordize the Jfet. As a result of forward biasing the decreased internal resistance has the potential to destroy Jfet.
This agrees with everything I have read about creating a stable current source. Of course I am unaware of how the matched, paralleled scheme helps in this area. It could be creating a stability factor that would not ordinarilty be present.
I don't think so, as otherwise the diff. pair couldn't get the swing amplified
nAr
Exactly, that is why I hope someone can point out where my ignorance is showing itself. That is assuming of course, that I am not totally ignorant....
, which is very possible
Except that the current through J1 cannot increase unless the current through R1 also increases, and it would also need somewhere to go.
Someone set me straight if I'm wrong, but with R4-8 placed as equal voltage dividers, all 4 jfets are biased at saturation. Their Vds at equilibrium is the same.
On a positive swing, as J1 attempts to increase current flow by lowering its internal resistance, its Vds will drop, forcing J2 to raise its Vds to compensate. This would also make the voltage at J3s source pin higher, pushing it into neg bias and pinching off current through J3 and allowing J4 to accept the increase in current from J1.
Please, we need constructive criticism.
Someone set me straight if I'm wrong, but with R4-8 placed as equal voltage dividers, all 4 jfets are biased at saturation. Their Vds at equilibrium is the same.
On a positive swing, as J1 attempts to increase current flow by lowering its internal resistance, its Vds will drop, forcing J2 to raise its Vds to compensate. This would also make the voltage at J3s source pin higher, pushing it into neg bias and pinching off current through J3 and allowing J4 to accept the increase in current from J1.
Please, we need constructive criticism.
Walt Jung has presented lot's of data on CCS performance. He shows the simple CCS jFET to perform rather well. It can be improved. The cascoded jFET is such an improvement. He describes the implementation in detail.
For performance, he probably means by high impedance
Is there also a way to cascode both diff. pair and current sources ?
For CCS and diff pair, I think that is what is achieved in the attachment of post #20 ...
What do you mean by VAS ?
Regards,
nAr
Hi,
VAS = Voltage Amplifier Stage.
Turns turns the current output from the Long Tail Pair (LTP) into a voltage output to drive the next stage, usually a current amplifier.
This 3stage amplifier is commonly referred to as Lin 3stage amp after Lin, the inventor.
post20,
the lower group of 4 bc5xx are cascoded CCS.
The jFET has a folded cascode which operates differently. I think PASS describes both of these cascode types.
VAS = Voltage Amplifier Stage.
Turns turns the current output from the Long Tail Pair (LTP) into a voltage output to drive the next stage, usually a current amplifier.
This 3stage amplifier is commonly referred to as Lin 3stage amp after Lin, the inventor.
post20,
the lower group of 4 bc5xx are cascoded CCS.
The jFET has a folded cascode which operates differently. I think PASS describes both of these cascode types.
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Dave, I built a channel and at first glance everything seemed to be great, until I swept the freq. I set it up for 5X gain balanced. There looks to be a first order bass rolloff on the bottom end starting around 150hz. I increased the input cap to 10uf to eliminate any doubt and put the scope before the outut cap with basically no change. Any suggestions or comments?
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