Bob Cordell Interview: Error Correction

[Bob Cordell]

Originally posted by andy_c
Here's a variation of Bob's switching circuit concept that uses no optos. This is just a conceptual idea - not shown is how to OR the detector outputs together to get a single trigger signal.

The zeners represent the amp's shunt reg, and ground corresponds to the amp's output node. As suggested by Bob earlier, the positive and negative sides of the shunt reg would each be shorted to the amp's output. In this case, there are two latches arranged in such a way that they can be triggered by complementary BJTs.

To simulate this in SPICE, the OFF keyword needs to be used with the latch transistors because of the bistable nature of the circuit.

Hi Andy,

Cool! I've also wondered about doing it with some kind of arrangement using triacs, but have not done it.

Cheers,
Bob

[syn08]

Originally posted by syn08


if anybody around succesfully ported the 2SK1530 and 2SJ201 models that Andy and Edmond worked on to PSpice, then I would appreciate a copy.

Never mind, I figured it out:

.SUBCKT 2SJ201 1 2 3
* Node 1 -> Drain
* Node 2 -> Gate
* Node 3 -> Source
***************************
.PARAM pi=3.1416
.PARAM Cgdmin=143p
.PARAM Cgdmax=2677p
.PARAM a=0.31548599
.PARAM B={(Cgdmin + 0.5 * pi * Cgdmax) / (1 + 0.5 * pi)}
.PARAM C={(Cgdmax - Cgdmin) / (1 + 0.5 * pi)}
M1 4 5 3 3 PMOS5
RG 2 5 1m
RD 1 4 1m
;RD 1 4 0.198
DDS 1 3 DDS
CGS 5 3 1414p
GGD 2 1 VALUE={ if( V(2,1) < 0, {-C * tanh( a * V(2,1) ) + B}, {-C * atan( a * V(2,1) ) + B} ) * DDT(V(2,1)) }
.MODEL PMOS5 PMOS ( LEVEL=5 L=2U W=0.5m
;+ EKVINT = 1
+ cox = 3.6e-4
+ xj = 2e-7
+ vto= -1.72 ; threshold voltage, adjust this value at will
+ gamma=6
+ phi=2.4
+ kp=8.5e-2
+ e0=2.0e+11
+ ucrit=2.67e+13
+ dl=0 dw=0
+ lambda=1.1305e5
+ ibn=1.0 iba=0 ibb=3.0e8
+ weta=0.0 q0=0 LK=2.9e-7
+ leta=0.0 rsh=0.0 )
************************************************** ********************
.MODEL DDS D( N=1.55178 IS=2e-8 RS=0.01 CJO=1544p M=0.4786242 VJ=0.423139 BV=200 )
************************************************** ********************
.ENDS

.SUBCKT 2SK1530 1 2 3
* Node 1 -> Drain
* Node 2 -> Gate
* Node 3 -> Source
***************************
.PARAM pi=3.1416
.PARAM Cgdmin=42.8114p
.PARAM Cgdmax=1216.887p
.PARAM a=0.31548599
.PARAM B={(Cgdmin + 0.5 * pi * Cgdmax) / (1 + 0.5 * pi)}
.PARAM C={(Cgdmax - Cgdmin) / (1 + 0.5 * pi)}
M1 4 5 3 3 NMOS5
RG 2 5 1m
RD 1 4 383m
DDS 3 1 DDS
CGS 5 3 850p
GGD 2 1 VALUE={ if( V(2,1) > 0, {C * tanh( a * V(2,1) ) + B}, {C * atan( a * V(2,1) ) + B} ) * DDT(V(2,1)) }
.MODEL NMOS5 NMOS (LEVEL=5 L=2U W=0.5m
;+ EKVINT = 1
+ cox = 7e-4
+ xj = 1e-8
+ vto=1.97 gamma=5.9999694 phi=3.4298218
+ kp=7.95e-2
+ e0=2.0568449051e+11
+ ucrit=2.6680517254825e+13
+ dl=0 dw = 0
+ lambda=1.1305e5
+ ibn=1.0 iba=0 ibb=3.0e8
+ weta=0.0 q0=0 LK=2.9e-7
+ leta=0.0 rsh=0.0 )
************************************************** **************************
.MODEL DDS D ( N=1.5517725590608 IS=2e-8 RS=0.009989 CJO=405.936p M=0.560182 VJ=2.403248 )
************************************************** **************************
.ENDS

[KSTR]

Regarding my output stage idea, this morning I now see something that uses the same concept, a feedback loop that just holds the added voltage drop across both output emitter resistors constant. Nobody less than Bruno "UcD" Putzeys designed it (together with Sander Sassen), a really straight design:
ExtremA, class-A strikes back?
I need to study that in detail.

And like I intend to do, they did it as a bridge design which I think is only of true benefit with class A.

Seems I'm not on a completely false track...

- Klaus

[x-pro]

Originally posted by KSTR
Regarding my output stage idea, this morning I now see something that uses the same concept, a feedback loop that just holds the added voltage drop across both output emitter resistors constant. Nobody less than Bruno "UcD" Putzeys designed it (together with Sander Sassen), a really straight design:
ExtremA, class-A strikes back?

Hi Klaus,

that particular idea is quite old and was published by Allison in 1972 according to Ben Duncan's book:

Cheers

Alex

[Edmond Stuart]

Originally posted by KSTR
Regarding my output stage idea, this morning I now see something that uses the same concept, a feedback loop that just holds the added voltage drop across both output emitter resistors constant. Nobody less than Bruno "UcD" Putzeys designed it (together with Sander Sassen), a really straight design:
ExtremA, class-A strikes back?
[snip]
- Klaus

Hi Klaus,

Also have a look at: E.M. Cherry, "A high quality audio power amplifier" in Monitor Porc. IREE Aust., Jan/Feb 1978, pp 1-8,
and referred at in Electronics World, June 1997, p. 476.

Cheers, Edmond.

[Edmond Stuart]

Originally posted by Edmond Stuart
..........
Now the last hurdle, i.e. the discrepancy of the THD figures. As Jan Didden has pointed out, "the ec loop encloses only the output devices", that is, not the drivers (see: http://www.diyaudio.com/forums/show...822#post1310822 ), I wonder whether the THD figures come closer to each other, if I manage to enclose the drivers too inside the EC loop.
................
Cheers, Edmond.

Originally posted by Bob Cordell
Hi Edmond,

That's a good point and I have already considered doing that by just using an extra set of emitter followers as the drivers instead of the diodes I show to get the voltages comfortably close to those that the Toshiba devices want. Not much difference between a diode and an emitter follower. The existing driver devices could then be run at a bit lower current, so the net disspation cost might not be that much. There are a couple of variations on how to do it, but that is the essence of it.

Cheers,
Bob

Hi Bob,

See below how I've eliminated the distortion of the drivers. Admittedly, it's a quick and dirty solution by using CFP stages and current sources, but nevertheless it gives optimal results.

Also notice that I've slightly adjusted the compensating caps so that the NFB loop in both circuits has the same Ft, 2.8MHz.

For results, see next post.

Cheers, Edmond.

[Edmond Stuart]

(continuation)

The THD20 in ppm at various power levels into 8 Ohm

1.0W : HEC: 22.28 NFB: 22.17
10 W : HEC: 54.55 NFB: 54.88
100W: HEC: 60.27 NFB: 54.00

As one can see, not only the THD figures are almost identical, but also the gain and phase plots of both amplifiers (see below) closely match each other.

I hope that these figures provide enough evidence that HEC is nothing more (or less) than NFB in disguise.

Cheers, Edmond.

[lumanauw]

Hi, Edmond,

Very interesting What is the input and output impedance of each approach?

[jan.didden]

Originally posted by Edmond Stuart
(continuation)

The THD20 in ppm at various power levels into 8 Ohm

1.0W : HEC: 22.28 NFB: 22.17
10 W : HEC: 54.55 NFB: 54.88
100W: HEC: 60.27 NFB: 54.00

As one can see, not only the THD figures are almost identical, but also the gain and phase plots of both amplifiers (see below) closely match each other.

I hope that these figures provide enough evidence that HEC is nothing more (or less) than NFB in disguise.

Cheers, Edmond.

Hmmm. Too good to be true, almost. Could it be that what is limiting the THD levels in each case, is what the two versions have in common - i.e. the input emitter followers (Q2,3, Q20,21)? These are outside the hec loop as well as the nfb loop if I'm not mistaken.

Jan Didden

[Edmond Stuart]

Originally posted by lumanauw
Hi, Edmond,

Very interesting What is the input and output impedance of each approach?

Hi Lumanauw,

The input and output impedance are frequency dependent, so I hope you don't mind that I'll show you them at only 20kHz.
Zi HEC: 2.17MOhm, NFB: 1.97MOhm.
Zo HEC: 3.3mOhm, NFB: 3.6mOhm.
At all other frequencies they are also almost identical.

Cheers, Edmond.