Simple Low Distortion JFET Buffer

Attached is a schematic and simulation results for a simple cascoded "Fetwhite" buffer. The simulation results were surprisingly good, so I did a hack job on one of my buffer modules to try it out in my test preamp. Audible results are excellent. The unit gain buffer is also a good gain match for my overall system.
I will need to wait until I'm back at work next year before I can really do any serious testing on the new circuit, as all the good gear is there. It will be interesting to see if the test results for THD are anywhere near as good as the simulation.

I plan to try out some simulations to check the difference between using a simple cascoded buffer and the White circuit. Last time I loooked, the White circuit had lower distortion, but the simple buffer would allow me to try a cascoded bipolar current sink instead of the JFET current sink current used here.
 

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I usually like to see buffers tested with Higher source impedance and Lower output load - otherwise you might as well skip the active stuff altogether

almost anything will look good with low source Z and high Z load - I think you will find large area, low noise fet's nonlinear input C limits high freq linearity with higher source Z
 
MikeB said:
Hi jcx !

You're right, it was bs to simulate like that... It's no problem for this circuit to reduce the load below 1k, but feeding it with a high impedance signal (22k in series with the v-source) distorted the signal at input with ~-72db (0.025%). Sorry for posting that... Wrenchone's circuit shows similar problems, but is better.

Mike

Mike,

WRT complimentary JFET buffer:

No need to have 4 devices as 2 will suffice.

Here are some actual measurements:

5V rms, 1k load, 150R source impedance, f=1kHz, THD = 0.023%

As the source Z increases the THD will increase especially
at higher frequencies due to the non linear cap of the Jfets.

5V rms, 100k load, 20k source Z, f=10kHz, THD = 0.22%

All above at suipplies +- 12V

Increasing supplies to +-24V lowers 0.22% to 0.06%.
The higher suplies help low the modulating cap non linearities.

All measurements were done with AP model 1

Cheers,

Terry
 
MikeB said:
Okay, but this done does the job... (topology from steven)

Even with 220k source impedance, loaded with 1k, distortions at ~-132db for 10khz,1v...

Mike

Hi Mike,

I really dig your follower circuit.... is that your idea??

It will not acheive anywhere near those numbers in real
life though.

You have 2k across 0.7V on the lower modulated CCS BJT.
So the upper bootstrap BJT is running at 0.35 mA quiescent.
This is not enough to cover the modulating +-1.4mA in the jfet
due to 1V into 1k load.

Further, in real life, these high gm jfets need more than 0.7V
S-D to work well as the cap is extremely non linear with these
small voltages across the device. IME => 3V is much better.

Thermal noise of 220k IP R is about 101dB below 1V . :confused:

Time to start verifying sims with real measurements :cool:



Cheers,

Terry
 
Perform a simulation on the following circuit description... I don't have any circuit drawing software on this computer, so bear with me:

Vdd goes through two 250 ohm resistors in series to the drain of Q1, whose gate is joined to Q2, and whose source is connected through a 10 ohm resistor to the drain of Q2.

The source of Q2 is connected through a 20 ohm resistor to the output, optionally bypassed with a high-quality capacitor of your choice. Its gate is connected through a stopping resistor (e.g. 221ohm) to the input.

The input is connected through a 50Kohm resistor to the output, a bootstrap configuration that should keep input impedance practically infinite, except for gate leakage and input capacitance.

The output is connected to the drain of Q3, whose gate is joined to Q4, and whose source is connected through a 10 ohm resistor to the drain of Q4.

The source of Q4 is connected through a 20 ohm resistor to Vss, and through a 22uF capacitor to the point between the 250 ohm resistors. Its gate is connected through two 25K resistors in series to ground, and through a 22uF capacitor to the drain of Q1. A 22uF capacitor between the source of Q4 and the point between the two 25K resistors completes the circuit.

Preferred transistors for Q2 and Q4 are low-Vgs devices with good matching. LS843 is excellent with regards to matching (SPICE model at www.linearsystems.com), but I'd prefer U401 from Vishay Siliconix.

As a last resort, use 2SK146, 2SK389 or matched 2SK369/2SK170, etc.

Q1 and Q3 should be matched too, but are less critical. 2SK246 is apparently a good choice, according to Borbely's site. The important thing is that they give enough Vds for the follower to operate in its saturation region.

Fiddle with the values, including using ideal voltage source sweeps to find the "perfect" Vds and Ids for the transistor you choose. Rs will need to be adjusted in some cases.

There are some transistors out there, including current production models from e.g. Toshiba, Fairchild, Linear Systems, InterFET and OnSemi that are suited to cascoding themselves. Match a quad to 1mV or so, and things could get really interesting ;)

Q1 and Q3 usually prefer 10-20V over them.

The circuit can be tuned according to preferences and requirements, and should work with closely matched depletion MOS, SiGa, GaAs, etc.. devices, given the right rails, resistors and caps.
 
Vdd goes through two 250 ohm resistors in series to the drain of Q1, whose gate is joined to Q2, and whose source is connected through a 10 ohm resistor to the drain of Q2.

The source of Q2 is connected through a 20 ohm resistor to the output, optionally bypassed with a high-quality capacitor of your choice. Its gate is connected through a stopping resistor (e.g. 221ohm) to the input.

The input is connected through a 50Kohm resistor to the output, a bootstrap configuration that should keep input impedance practically infinite, except for gate leakage and input capacitance.

The output is connected to the drain of Q3, whose gate is joined to Q4, and whose source is connected through a 10 ohm resistor to the drain of Q4.

The source of Q4 is connected through a 20 ohm resistor to Vss, and through a 22uF capacitor to the point between the 250 ohm resistors. Its gate is connected through two 25K resistors in series to ground, and through a 22uF capacitor to the drain of Q1. A 22uF capacitor between the source of Q4 and the point between the two 25K resistors completes the circuit.

Sorry, but I cant get it, at all.
:)
 
MikeB said:


Hi Terry, no, it is not my idea, this principle was posted by steven. It is about the active device having constant voltage AND constant current.

Mike

Yes, understood.

There are also some of tube based variants, I think they are
called a white follower.

However this is the first that I had seen with the CCS 'adjustment'
current taken from a shunt bootstrapping BJT.

Cheers,

Terry
 
lineup said:
Sorry, but I cant get it, at all.
:)

Okay. I just realized I can do ASCII art here too. I'll try to post something good later.

First, chew on this very simple buffer:
Code:
[LIST]
[*]
[*]                   --- Vdd
[*]                    |
[*]                    +--|
[*]                Q2a    |
[*]                    +--|<--+
[*]                    |      |
[*]                    +----+ R2
[*]                    |    | |
[*]                 |--+    | D1a
[*]             +-->|   Q1a | |
[*]             |   |--+------+
[*]             |      |    |
[*]             +--C1--+    C2
[*]             |      |    |
[*]             R2     R1   |
[*]             |      |    |
[*]    IN C--+--+--R3--+----+-------+
[*]       |  |         |            |
[*]       |  R         +--|   OUT C-+
[*]       |  |      Q2b   |       |
[*]       +--+         +--|<--+   |
[*]          |         |      |  ===
[*]         === +------+      R2  =
[*]          =  |      |      |
[*]             C2  |--+      D1a
[*]             |   |    Q1b  |
[*]             +-->|--+------+
[*]             |      |
[*]             +--C1--+
[*]             |      |
[*]             |      R1
[*]             |      |
[*]             +------+
[*]                    |
[*]               Vss ---
[*]
[/LIST]

  • R is the desired input impedance. It may be omitted if the input is in the range Vss<Vin<Vdd.
  • R1 is the self-bias source resistance for the desired output current. Just decide on the idle current you want, then use a trimpot to find the fixed value. Or, if you don't care, as long as DC offset is low, you can use dual monolithic JFETs, and just pick a value that doesn't burn it out.
  • R2 is the gate stopper. Nelson uses 221R on his MOS amps. Many people use 10R, or even nothing. If you have no oscilloscope, use 1K.
  • R3 is the bootstrap. Set it to 100K or something. It'll pretend to be in the megohm range.
  • C1 is on the order of 10-100pF, and swamps the inherently nonlinear Ciss capacitance.
  • C2 is 1uF NP0 ceramic, or whatever you can afford. High frequency (>100MHz) voltage/temperature/load/frequency invariant nonpolar caps only.
  • D1 is a zener diode meant for 1-1000pA current. It should be 4-20V (specifically 2Vp>Vdg>20V, or even 3Vp), depending on Q1. 8-10V is an OK guess in this application.
  • Q1 is the gain JFET. Make it low noise, high current (Idss of at least 10 * Iout), high Gfs (at least 2*Iout/Vout), low Goss (at most .3*Gfs), linear above Vds<2Vp when 0.5<|Vgs|<|.9Vp|>, and nicely matched (|VgsQ1a-VgsQ1b| < 10mV). You get monolithic ones with 1-100mV max difference.
  • Q2 is the cascode JFET. Make it high current (IdssQ2 > 2IdssQ1), low Goss (GossQ2 < .3GossQ1), high Vp and (Igsx < Iout/1000). Matching should be 100mV or better.
  • Vdd/Vss is +/- supply rails, and should usually be 15V-24V or more.

I think that covers a basic buffer with <1mV offset and (with the right transistors etc.) up to 1Arms.

A simplified version with closely matched components, and well dimensioned, gives <100ppm THD+N (2nd/3rd harmonic).
 
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MikeB said:
Hmm, sorry if i am annoying, but why that complex ? :D
Okay, mine has 4 jfets, but much less caps and resistors, and is DC-coupled. With matched jfets the dc-offset will go away.
Distortion levels are equal, 0.0001%,-120db. BW is -3db >1mhz.

Mike


Mike,

I find your buffer ( http://www.diyaudio.com/forums/showthread.php?postid=803029#post803029 ) most elegant as it is a straight forward, open loop design with no 'hidden' feedback loops. It is very clean, astonishingly so. I wonder what the distortion rise is with level? How does the freq response look without the compensation? What is the Zout? I know, questions, questions...

Thanks,
Jan Didden
 
Hi Jan, yes, i loved that circuit at the beginning, looks very elegant.
But jcx took me back to the ground, i forgot to check its behaviour with high ohm source impedance. What good is a buffer if it starts to distort when fed from a high impedance source ?

To your questions, i don't remember exactly, but zout was ~10ohms, freq response flat above 100khz (no peaks, no resonances,-3db at 1mhz). Distortions rised when 2nd stage left ClassA operation. I don't remember more facts on this circuit.

That's why i showed the 2nd one, really doing it's job.

Mike
 
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Joined 2002
Paid Member
MikeB said:
Hi Jan, yes, i loved that circuit at the beginning, looks very elegant.
But jcx took me back to the ground, i forgot to check its behaviour with high ohm source impedance. What good is a buffer if it starts to distort when fed from a high impedance source ?

To your questions, i don't remember exactly, but zout was ~10ohms, freq response flat above 100khz (no peaks, no resonances,-3db at 1mhz). Distortions rised when 2nd stage left ClassA operation. I don't remember more facts on this circuit.

That's why i showed the 2nd one, really doing it's job.

Mike


OK, thanks. I realise the input Z issue, but I wouldn't use it anywhere near 22k Zin - probably not more than a few k.
And I have a reason to remain open loop, so I may still try this one out.

Jan Didden
 
wrenchone said:
Attached is a schematic and simulation results for a
simple cascoded "Fetwhite" buffer.
Audible results are excellent.
The unit gain buffer is also a good gain match for my overall system.
...
Last time I loooked, the White circuit had lower distortion, but the simple buffer would allow me to try a cascoded bipolar current sink instead of the JFET current sink current used here.



so is anyone of these 3 buffer suggestions still alive and in good health?

1. wrenchone
schematic: http://www.diyaudio.com/forums/attachment.php?s=&postid=802626&stamp=1135983661
2. MikeB ( by steven )
schematic:
http://www.diyaudio.com/forums/attachment.php?s=&postid=803157&stamp=1136057934
3. angel
schematic:
http://www.diyaudio.com/forums/showthread.php?postid=808501#post808501

**********************************************


If they are dead
I have my own 'Super Easy Done buffer.
See my attached circuit!


This version takes total 9.5 mA supply current.
As can be seen, this setup is optimized for
Perfect 25.000 Hertz squarewave
at +/-2.0 Volt into 2k2 loading.


To achieve this the 3dB bandwidth is set to:DC to 800.000 Hertz

I will attach AC Analysis, frequency sweep & phase angle figures
in next post!
 

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