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Old 30th December 2005, 10:01 PM   #1
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Default Simple Low Distortion JFET Buffer

Attached is a schematic and simulation results for a simple cascoded "Fetwhite" buffer. The simulation results were surprisingly good, so I did a hack job on one of my buffer modules to try it out in my test preamp. Audible results are excellent. The unit gain buffer is also a good gain match for my overall system.
I will need to wait until I'm back at work next year before I can really do any serious testing on the new circuit, as all the good gear is there. It will be interesting to see if the test results for THD are anywhere near as good as the simulation.

I plan to try out some simulations to check the difference between using a simple cascoded buffer and the White circuit. Last time I loooked, the White circuit had lower distortion, but the simple buffer would allow me to try a cascoded bipolar current sink instead of the JFET current sink current used here.
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Old 31st December 2005, 01:54 AM   #2
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I did a simulation of the circuit without the R and C for the White follower, and the distortion was over 10X higher (0.009%, less pleasant harmonic distribution). I think I'll keep the White follower and just make sure my power supply is very clean...
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Old 31st December 2005, 02:17 PM   #3
MikeB is offline MikeB  Germany
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Hmm, sorry if i am annoying, but why that complex ?
Okay, mine has 4 jfets, but much less caps and resistors, and is DC-coupled. With matched jfets the dc-offset will go away.
Distortion levels are equal, 0.0001%,-120db. BW is -3db >1mhz.

Mike
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Old 31st December 2005, 04:28 PM   #4
jcx is offline jcx  United States
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I usually like to see buffers tested with Higher source impedance and Lower output load - otherwise you might as well skip the active stuff altogether

almost anything will look good with low source Z and high Z load - I think you will find large area, low noise fet's nonlinear input C limits high freq linearity with higher source Z
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Old 31st December 2005, 05:41 PM   #5
MikeB is offline MikeB  Germany
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Hi jcx !

You're right, it was bs to simulate like that... It's no problem for this circuit to reduce the load below 1k, but feeding it with a high impedance signal (22k in series with the v-source) distorted the signal at input with ~-72db (0.025%). Sorry for posting that... Wrenchone's circuit shows similar problems, but is better.

Mike
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Old 31st December 2005, 06:38 PM   #6
MikeB is offline MikeB  Germany
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Okay, but this done does the job... (topology from steven)

Even with 220k source impedance, loaded with 1k, distortions at ~-132db for 10khz,1v...

Mike
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Old 31st December 2005, 10:58 PM   #7
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Quote:
Originally posted by MikeB
Hi jcx !

You're right, it was bs to simulate like that... It's no problem for this circuit to reduce the load below 1k, but feeding it with a high impedance signal (22k in series with the v-source) distorted the signal at input with ~-72db (0.025%). Sorry for posting that... Wrenchone's circuit shows similar problems, but is better.

Mike
Mike,

WRT complimentary JFET buffer:

No need to have 4 devices as 2 will suffice.

Here are some actual measurements:

5V rms, 1k load, 150R source impedance, f=1kHz, THD = 0.023%

As the source Z increases the THD will increase especially
at higher frequencies due to the non linear cap of the Jfets.

5V rms, 100k load, 20k source Z, f=10kHz, THD = 0.22%

All above at suipplies +- 12V

Increasing supplies to +-24V lowers 0.22% to 0.06%.
The higher suplies help low the modulating cap non linearities.

All measurements were done with AP model 1

Cheers,

Terry
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Old 31st December 2005, 11:37 PM   #8
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Quote:
Originally posted by MikeB
Okay, but this done does the job... (topology from steven)

Even with 220k source impedance, loaded with 1k, distortions at ~-132db for 10khz,1v...

Mike
Hi Mike,

I really dig your follower circuit.... is that your idea??

It will not acheive anywhere near those numbers in real
life though.

You have 2k across 0.7V on the lower modulated CCS BJT.
So the upper bootstrap BJT is running at 0.35 mA quiescent.
This is not enough to cover the modulating +-1.4mA in the jfet
due to 1V into 1k load.

Further, in real life, these high gm jfets need more than 0.7V
S-D to work well as the cap is extremely non linear with these
small voltages across the device. IME => 3V is much better.

Thermal noise of 220k IP R is about 101dB below 1V .

Time to start verifying sims with real measurements



Cheers,

Terry
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Old 1st January 2006, 12:12 AM   #9
angel is offline angel  Norway
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Perform a simulation on the following circuit description... I don't have any circuit drawing software on this computer, so bear with me:

Vdd goes through two 250 ohm resistors in series to the drain of Q1, whose gate is joined to Q2, and whose source is connected through a 10 ohm resistor to the drain of Q2.

The source of Q2 is connected through a 20 ohm resistor to the output, optionally bypassed with a high-quality capacitor of your choice. Its gate is connected through a stopping resistor (e.g. 221ohm) to the input.

The input is connected through a 50Kohm resistor to the output, a bootstrap configuration that should keep input impedance practically infinite, except for gate leakage and input capacitance.

The output is connected to the drain of Q3, whose gate is joined to Q4, and whose source is connected through a 10 ohm resistor to the drain of Q4.

The source of Q4 is connected through a 20 ohm resistor to Vss, and through a 22uF capacitor to the point between the 250 ohm resistors. Its gate is connected through two 25K resistors in series to ground, and through a 22uF capacitor to the drain of Q1. A 22uF capacitor between the source of Q4 and the point between the two 25K resistors completes the circuit.

Preferred transistors for Q2 and Q4 are low-Vgs devices with good matching. LS843 is excellent with regards to matching (SPICE model at www.linearsystems.com), but I'd prefer U401 from Vishay Siliconix.

As a last resort, use 2SK146, 2SK389 or matched 2SK369/2SK170, etc.

Q1 and Q3 should be matched too, but are less critical. 2SK246 is apparently a good choice, according to Borbely's site. The important thing is that they give enough Vds for the follower to operate in its saturation region.

Fiddle with the values, including using ideal voltage source sweeps to find the "perfect" Vds and Ids for the transistor you choose. Rs will need to be adjusted in some cases.

There are some transistors out there, including current production models from e.g. Toshiba, Fairchild, Linear Systems, InterFET and OnSemi that are suited to cascoding themselves. Match a quad to 1mV or so, and things could get really interesting

Q1 and Q3 usually prefer 10-20V over them.

The circuit can be tuned according to preferences and requirements, and should work with closely matched depletion MOS, SiGa, GaAs, etc.. devices, given the right rails, resistors and caps.
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Old 1st January 2006, 12:21 AM   #10
lineup is offline lineup  Sweden
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Quote:
Vdd goes through two 250 ohm resistors in series to the drain of Q1, whose gate is joined to Q2, and whose source is connected through a 10 ohm resistor to the drain of Q2.

The source of Q2 is connected through a 20 ohm resistor to the output, optionally bypassed with a high-quality capacitor of your choice. Its gate is connected through a stopping resistor (e.g. 221ohm) to the input.

The input is connected through a 50Kohm resistor to the output, a bootstrap configuration that should keep input impedance practically infinite, except for gate leakage and input capacitance.

The output is connected to the drain of Q3, whose gate is joined to Q4, and whose source is connected through a 10 ohm resistor to the drain of Q4.

The source of Q4 is connected through a 20 ohm resistor to Vss, and through a 22uF capacitor to the point between the 250 ohm resistors. Its gate is connected through two 25K resistors in series to ground, and through a 22uF capacitor to the drain of Q1. A 22uF capacitor between the source of Q4 and the point between the two 25K resistors completes the circuit.
Sorry, but I cant get it, at all.
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