Spice: how to set IDSS etc?

[bear]

Being slow to the dance, I just downloaded Linear Tech's SwcadIII and have been playing about with it...

Among the many things that are not mentioned or clear with or without the help file is how does one go about "setting" the IDSS for a JFET, or similarly Vgs for a Mosfet.

I see a great number of parameters for a given JFET, but none seems to directly correspond to IDSS (for example) - or else they're calling it something else.

Yes, I understand about chosing specific devices from the available devices, and/or the possibility of adding in devices (from someplace or another...), but for simplicity at this point I'd just as soon massage these two parameters for existing models for the sake of just making given circuits work according to what a pen and paper design says that they ought to.

Any input, or citations for sites that can provide this sort of info, would be appreciated.

_-_-bear

[Mr Evil]

For JFETs you want to change vt0, which is the turn-off gate-source voltage. Also of use is beta, which is the transconductance. Both of those will change Idss.

[bear]

Ok, now all we need is a formula that relates the Beta & Vto to IDSS! Or a citation where I can find this info myself...

This is an example of two of the "standard" JFET models:

.model 2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311

.model 2N4338 NJF(Beta=781u Betatce=-.5 Rd=1 Rs=1 Lambda=1.167m Vto=-.6606 Vtotc=-2.5m Is=114.5f Isr=1.091p N=1 Nr=2 Xti=3 Alpha=506.8u Vk=251.7 Cgd=2.8p M=.2271 Pb=.5 Fc=.5 Cgs=2.916p Kf=2.918E-18 Af=1 mfg=Fairchild)

_-_-bear

[andy_c]

Hi bear,

From Massobrio and Antognetti, here is the equation in SPICE form for the JFET drain current in the saturated region (not analogous to BJT saturation):

I_D=beta*(V_GS-V_TO)²*(1+lambda*V_DS)

from which you can calculate I_DSS.

[Randy Knutson]

Hi,
If you're using LTspice you should also join the LTspice forum on yahoogroups.com [very active and helpful!!!] Look through the archives your question has probably been answered at least a dozen times.

Good Luck!
-=Randy

[bear]

Gosh, I really don't like Yahoo's groups... but I will join anyhow.

Here's a really odd FFT result from LT's spice... the source is simply the internal virtual AC generator with a 100k load! I'm baffled as to why it should show any harmonics whatsover??

One is a 2000Hz source, the other is a 2200 Hz. source, the 1kHz source looks far worse!

_-_-bear

[SkyChu]

Have you turned off compression ( Tools>Control Panel>Compression ) ?

[heater]

I have been fighting with the FFT problem as well recently. Seemed every schematic had different harmonics on it's sine wave generators and is very sensitive to stop time and maximum time step (in the edit simulation command dialog box).

Now turning off compression, using a stop time of 100ms and a time step of 0.5uS I can get a plain generator with those spikes down 140db.

Trouble is this puts up the time it takes for simulation to complete which on my old 266MHz machine can be considerable.

Cheers for the tip.

[jcx]

LtSpice default compression of analysis data is inconvenient, remembering to disable it in the control panel menu every time you restart the program isn't reliable (for me anyway)

I add (or copy to actually) a spice directive line to all of my schematics:

.param plotwinsize=0

[Tom2]

jcx said
I add (or copy to actually) a spice directive line to all of my schematics:
.param plotwinsize=0

jcx,

I think it should be

.options plotwinsize=0


Also the .raw and .fft files associated with the schematic can be large. Usually after playing around with the schematic, I delete them to free up hard drive space and I leave the original .asc file.

tom