Cascode JFET IPS oscillation - getting crazy

[Bensen]

I've started this thread will I'm pulling my hair on this.

Following case:
I have prototyped the amp according circuit below (current status), without the bipolar output stage. Test speaker is connected to driver outputs = lateral fets with source resistors of R0.22.

1 . First build was with BJT cascode (2SC2911/2SA1209)

4mA Jfet bias (8ma "Tail") ==> 100KHz square wave was near to perfect
6mA Jfet bias ==> amp gets unstable when touching with DMM probe on everything in contact with the IPS, even when touching the power supply rails on the PCB.

​

My goal is something like 7 to 8mA IPS bias, with Vds of 7..9Volts.

What have I done:

1. Removed the VAS cascodes ==> NOK
2. Removed the CCS for he IPS cascodes to resistor devider ==> A bit better
3. Added extra decoupling caps on the PCB ==> NOK
4. Added big base stoppers close to cascodes ==> at about 1K2 it seemed to work, however according spice I'm loosing quite some gain margin? Correct??
5. Added all kind of bypass caps on the resistor divider, over resistors or to ground ==> definitely NOK
6. Changed resistor divider values with a factor of 10 with keeping same ratio offcourse ==> NOK
7. Changed resistor divider with reference to GND instead of source connection of jfets (hawksford) ==> NOK
8. Tried other BJT's for cascode ==> NOK
9. Replaced BJT cascode transistors to FET's (610/9610) ==> NOK
10. Gate resistors R0 or R470 ==> identically and NOK​

What to try now? I'm out of options for the moment.
I can touch with the DMM probes anything else on the PCB wihtout a problem, but touching the power supply and GND traces ==> Big hum throught the speaker and big output offset.

 

[rayma]

I've started this thread will I'm pulling my hair on this.

So this circuit is open loop, with no nfb connected, and no output stage?
Most fets will require a gate resistor for stability, regardless of what Spice says.
What does NOK mean?

 

[Bensen]

OK, will add the correct circuit tomorrow. The r0,22 lat fet source resistor are connected to FDB point of the input stage. And the zobel network is connected on the "new" output.

All fet's have gate stoppers as far as I understand.. Does the resistor divider for the cascode has the same effect as a gate stopper?

 

[rayma]

All fet's have gate stoppers as far as I understand.. Does the resistor divider for the
cascode have the same effect as a gate stopper?

All eight of the input fets should each have a gate resistor connected directly at the gate.
Only the "upper" device of each pair has a gate resistor in the diagram, and even those
resistors that are present are far too small in value.

 

[jcx]

the IRF power devices for cascode are rather odd - how about someting only one order of magnitude bigger than the jfets

 

[nauta]

Hi

Regardless of whether R16,182 are grounded or tied to the jfet sources, shouldn't there be a cap across each? In the "grounded" case, this will place the reference for the mosfet gates at AC ground. For the "CM"-case, it will place the gates at the same AC potential as the jfet sources.

As others have stated, the 100mR gate-stops are a joke - should be higher in this application. The jfets might benefit from gate-stops too, as in all cases the stop resistor works against the internal capacitance of the device to form a HF-rolloff. The divider R cannot quite do this, especially when working against two devices.

I believe C51 needs a complementary cap for the other side ofd the circuit. Although Self has suggested that "asymmetric compensation works the same as symmetric", it certainly does not feel right and I've never seen a real symmetric circuit with asymmetric compensation. Sometimes the littlest things make the difference.

 

[nigelwright7557]

c1 and c2 are far too small.
The circuit needs damping more.

 

[mlloyd1]

Are the posted values for R18 and R181 (gate resistors for the upper cascoding MOSFETs) correct at 0.1 ohms? If so, they are way too small.

You may also want to consider gate resistors for each of the small signal JFETS in the input diff amps.

Good luck!
mlloyd1

 

[Bensen]

All eight of the input fets should each have a gate resistor connected directly at the gate.
Only the "upper" device of each pair has a gate resistor in the diagram, and even those
resistors that are present are far too small in value.

Will add again gate stoppers to the cascode devices first and than on the Jfets. Any idea about the value for these?

the IRF power devices for cascode are rather odd - how about someting only one order of magnitude bigger than the jfets

Well, my goal is 8ma bias and with about 45v over the cascode, this gives 0.36W power dissipation. My first try with TO126 bjt's learned me that this power dissipation was on the edge (+-50°C with a room temp of only 15°C!) without heatsinks added to the cascodes. John Curl is using the 610/9610 as cascode devices for the IPS in his HCA3500 and JC1 amp's. These are proven designs.

Hi

Regardless of whether R16,182 are grounded or tied to the jfet sources, shouldn't there be a cap across each? In the "grounded" case, this will place the reference for the mosfet gates at AC ground. For the "CM"-case, it will place the gates at the same AC potential as the jfet sources.

As others have stated, the 100mR gate-stops are a joke - should be higher in this application. The jfets might benefit from gate-stops too, as in all cases the stop resistor works against the internal capacitance of the device to form a HF-rolloff. The divider R cannot quite do this, especially when working against two devices.

I believe C51 needs a complementary cap for the other side ofd the circuit. Although Self has suggested that "asymmetric compensation works the same as symmetric", it certainly does not feel right and I've never seen a real symmetric circuit with asymmetric compensation. Sometimes the littlest things make the difference.

The 100mR where there just to play with the value in spice, at this moment no gate stoppers are placed. Will add them again and play with the value.
Regarding the bypass caps, as mentioned in post 1: I really tried numerous things with different kind of film caps and values. All lead to even worse unstability and bigger humm.

c1 and c2 are far too small.
The circuit needs damping more.

Well the amp was stable using 4ma Jfet bias running square waves up to 200kHz 30Vpp in a 8R/100n load. I know Fet models suck big time in spice, but with the build as like circuit below, PM= 85° and GM= 29dB.


Next option will be:
1 increase gate stoppers from VAS lat fets from 33R to 100R
2 add gate stoppers to the 610/6910 cascode fets
3 add gate stoppers to the jfets.

 

[juma]

Bensen, putting 100R between cascoded transistor's drain/colector and source/emitter of the cascode usually cures the oscilation problem in similar designs.

 

[nauta]

Hi

juma's idea is a good one. I had to use 348R in a triple cascode I mnade using three BC560Cs in series. The R is only needed between the bottom device and the one above it.

In the frequency plot, there was a Bode shelf with a small upturn on its corner and adding the resistor flattened that spike.

Bonsai reprted that he had to use a base-stop from the cascode voltage reference, but then further added small caps to ground from the base-stop - which made it no longer a base-stop: rather, the RC became a LP-filter. A base-stop is still beneficial in that case. I tried those methods in my triple and they made things worse, where the emitter-stop (or collector-stop?) did the trick.

Where common values like 100R are good starting points, they can seem very arbitrary and you really have to go much higher or lower to see what the effect is.

Gate-stops for the mosfets or jfets are typically 1k - again, seemingly arbitrary but a sim will show its effect.

 

[Bensen]

Making small progress

What have I done:

1/ Gate stoppers VAS Lat Fets: 33R ->100R = no difference
2/ 1K Gate stoppers added to Fet cascodes IPS = better result. Can measure over 1R Source resistors and drain resistors of jfets without hum. But sill huge hum when touching power supply traces on PCB with measuring probes DMM!
3/ Added 100N MKT film caps from midpoint resistor divider cascode to GND -> directly low frequency hum +- 100Hz ==> definetely NOK

Next actions:
4/ add 100R gate stoppers to jfets
5/ add the resistors between jfets and fet cascodes as per Juma and Nauta proposal.

 

[Bensen]

Anyone an idea what the purpose is of the 10R resistors before the sources of the 610/9620 VAS fet's in the parasound JC1 front end, see picture.
BTW: vas mosfets are wrongly connected to the IPS as far as I understand.

http://www.diyaudio.com/forums/atta...s-blowtorch-preamplifier-ii-input_r5-copy-pdf

 

[nauta]

I've started this thread will I'm pulling my hair on this.


I can touch with the DMM probes anything else on the PCB wihtout a problem, but touching the power supply and GND traces ==> Big hum throught the speaker and big output offset.

Have you checked that the 10R ground-link-isolate resistor is intact?

Do you have a scope? All the tweaking you are doing should be done with a bench load and scope NOT with speakers. If you MUST use a speaker, it would be a good idea to capacitively couple it.

When testing the gate-stop effects you have to use much higher values than you tried. otherwise it is a wasted effort.

This circuit seems like an attempt at being "all-fet" except for the BJT cascodes of the second stage. Is there a source or original prototype you are following?

 

[Bensen]

Problem solved...BUT

What have I done

1. Insert 100R resistors between Jfet Drains and Fet cascode sourcec ==> result Not OK (NOK), still hum when measuring on PCB power supply traces
2. increase these resistors to 330R ==> hum completely gone!!!
3. now reduced VAS Lat fet gate stoppers from R100 back to R33 ==> hum came back and thus increased them back to 100R.
4. Removed 1K gate stoppers from Fet IPs Casodes ==> all still OK


Edit: below text is wrong, something went wrong during simulation, I checked again because I could not image the impact between the resistors and ULGF
--------
BUT, with simulating, it seems those 330R resistors decrease ULGF and thus OLG BW quite a lot. Damn!
Now, what I'm planning to do is, play with the FET IPS cascode gate stoppers to quite high values (2k2...4K7) and those 330R resistors, with the goal to decrease the 330R and increase ULGF.
--------

Now for the fun, I wanted to check whether the JFET bias has really an influence on stability/hum. I increased the bias to 7ma ==> and YES hum starting to appear again when measuring on the power supply PCB traces.


Another question. When using 2SK389/109BL Jfet with on idss of around 9mA, has anyone an idea about the difference in THD or influence on harmonic profile when using 4mA vs 8ma bias? An no I'm not having GR types, only 20pairs matched BL's.

 

[Bensen]

Have you checked that the 10R ground-link-isolate resistor is intact?

Do you have a scope? All the tweaking you are doing should be done with a bench load and scope NOT with speakers. If you MUST use a speaker, it would be a good idea to capacitively couple it.

When testing the gate-stop effects you have to use much higher values than you tried. otherwise it is a wasted effort.

This circuit seems like an attempt at being "all-fet" except for the BJT cascodes of the second stage. Is there a source or original prototype you are following?

Yip, 10R is still intact.
Yes I have a scope (2channel, 60Mhz only). For square wave testing I use a dummy load, however when playing around with different values I prefer to use a speaker to also hear the effect regarding hum and other strange sounds.

Indeed, it seems like an "all-fet" attempt, but it is not the intention. The circuit you seen in for example the above post is without the output stage (see post 1). The output stage consists out of 5pairs 2SC2922/2SA1216 BJT's.

 

[nauta]

Hi

The 100kHz oscillation mentioned in post-1 is in the sim? or just the physical amp? or both?

Having just the mosfet driver as the "output" will be quite different than having the BJT output stage attached as far as the sim and real amp go. If the oscillation exists in the sim, I would leave the whole amp intact and compensate it as a complete circuit. Intuitively it should be better to do as you are doing, working on just the voltage-gain portion.

Linear tech app notes suggest that when dealing with oscillations, you apply bandaids until the oscillation stops, leaving all in place until that stop. Then go back and remove them in the order they were applied to see which did the trick. Oscillation is usually layout-related, so stop-resistors must be right at the device they are intended to tame; power wiring should be arranged correctly; related ground/signal paths should be routed together, and so on. These things can make the amp unstable even if the sim was stable.

Another thing comes to mind: Particularly with resistive current sources in the front-end, dialling the voltage up can cause oscillation at low voltages since the gm of the circuit is not balanced to the compensation. I've seen this a few times in real circuits.

 

[Bensen]

Hi Nauta,

I haven't mentioned 100kHz oscillation in post1. What I ment here was that square wave testing on 100kHz give very good result.

In sim the amp looks relatively stable with Phase Margin between 80° and 90° with a gain margin of +-18dB. But both vary quite alot dependant on mosfet spice models.

Now with simulating the optimized front end including the big BJT output stage, it seems that both the gate stoppers values of the IPS cascode as well as the resistors between Jfet's and cascode have a big influence on ULGF.
330R between Jfet drain and cascode source ==> ULGF 1.5mHz (front end stable with 6.5ma bias)
0R...==> 3mHz (front end stable with 4..5ma bias)

I tend to reduce IPS bias back to 4..5mA, where all was stable without any extra resistor. However I will add for certainty gate stoppers of R220 direct under Fet body and cut the gate wire.



I've learned quite a lot and made some documentation for mysef for future projects. Thanks guys.

BTW: the tested front end is actuilly an all-fet amplifier and must say it really sound marvelous compared to anything I heard before.

 

[nauta]

Hi

You seem to be more concerned with the open-loop gain band-width than THD. Have you checked the THD at 1kHz and 20kHz?

In my limited skill with the simulator, all of which I learned from Bob Cordell's book - thanks, Bob! - I try to make the closed-loop bandwidth as wide as possible with as flat a phase response as I can achieve in that bandwidth. I believe that the phase must be very flat if the feedback is to eliminate or reduce higher harmonics for high-frequencies. I haven't seen anyone discuss this specific aspect of phase response vs THD.

Do you think that the folded-cascode of your input stage contributes to the sound you hear? It seems to me that it would require an extremely clean and/or well-regulated rails since the signal is "bounced off" of them.

 

[PRR]

...I try to make the closed-loop bandwidth as wide as possible with as flat a phase response as I can achieve in that bandwidth. I believe that the phase must be very flat if the feedback is to eliminate or reduce higher harmonics for high-frequencies. I haven't seen anyone discuss this specific aspect of phase response vs THD.

If you are on the 6dB/oct slope, the phase is 90 degrees, which is nearly as good as zero.

There is ALWAYS a slope (no amplifier runs to infinite frequency), so this is about as good as it gets. (Some advanced techniques can shift benefit from ultrasonic zones into the audio zone.)

Do you think that the folded-cascode of your input stage contributes to the sound you hear? It seems to me that it would require an extremely clean and/or well-regulated rails since the signal is "bounced off" of them.

If the collector/drain impedance is infinite, the rail-nodes can bop up and down all they like and no effect.

We never get infinite collector/drain impedance, but it can be so high that it is not a concern.