Cascode JFET IPS oscillation - getting crazy

[Walkalone]

Congratulation, Bonsai. You fixed your trouble.
So, what cause that oscillation? I want to known exactly reason. Many other projects biased LTP higher but there is no any issue same as that.

 

[Bensen]

Hi

You seem to be more concerned with the open-loop gain band-width than THD. Have you checked the THD at 1kHz and 20kHz?

In my limited skill with the simulator, all of which I learned from Bob Cordell's book - thanks, Bob! - I try to make the closed-loop bandwidth as wide as possible with as flat a phase response as I can achieve in that bandwidth. I believe that the phase must be very flat if the feedback is to eliminate or reduce higher harmonics for high-frequencies. I haven't seen anyone discuss this specific aspect of phase response vs THD.

Do you think that the folded-cascode of your input stage contributes to the sound you hear? It seems to me that it would require an extremely clean and/or well-regulated rails since the signal is "bounced off" of them.

Indeed, one of the main goals is high open loop bandwidth together with relative high class A output (+-6W/8R).
THD is not what I'm interested in (1K/1W = +-0.0001 and 20K/1W is +-0.001), the harmonic profile is. See FFT 1W/1K below.



Regarding the hum issue when measuring on the power supply pcb traces.
Could it be that not the IPS Bias is causing the problems, but the rather low drain/collector resistor of the IPS??
4mA Bias gives an load resistor of about 600 - 700Ohms, where 7mA will be about 350 to 400Ohm? Shoul I try increasing the loading resistore of the IPS?

 

[Bensen]

Solved

As mentioned in previous post.
I have increased VAS degeneration from 56R to 220R and off course had to increase VAS loading resistor, to maintain bias currents. This is without the resistors between de Jfet drains and Mosfet sources of the cascodes, and without base stoppers to the FET cascodes.

No I can put my measuring probes everywhere on the PCB without a single problem/hum.


Result soundwise: well compared to my other amp, the difference is less big then it was with the 56R VAS degeneration. It looks like lowering the VAS degen makes the amp more musical (probably higher THD). Next test is lowering the VAS degen.

 

[Bensen]

VAS cascode deleted

Status from previous post seemed to be fine, but I forgot one thing. When changing the VAS hawksford cascode to standard cascode (referenced to rails) I left the 6.2 zener in place as voltage reference, with as result a Vds of only +-1V for the lateral FET's. I did notice this a few days ago.

Been playing with higher zener voltages, standard VS hawksford cascode...
nothing gave me good enough result.

THUS, I decided to remove the cascodes for the lateral VAS FET's completely.
Now all is fine.

Datasheets for the 2SK216+2SJ79 tell's me that cascoding these is not a must.
First of all they are already laterals with small capacitances which vary not that much compared with vertical FET's with changing Vds. And biasing them on 20..30ma, both look relatively compliments. (see below). I am doubting whether to try it IRF710/6910 combo?
Any comments/experience regarding 216/79 vs the vertical fets?