Ultra-low distortion with low complexity is more or less my objective too and I also find two (ish) pole input inclusive compensation effective.
We seem to be in accord here too. Lower emitter resistors for low noise and the two-pole schemes can use the extra loop gain, a perfect fit.
I use complementary IPS to lower the noise another 3 dB and accept the few extra transistors. It's a trivial financial cost and conceptually barely more complicated, basically paralleled transistors but with the benefits of input bias current cancellation, thermal balance and a symmetrical board layout for some cancellation of parasitics and stray pick-up.
On the contrary, I started the thread and no-one seems very interested in the GFT except for one joke, at least a bit funny.
I will just have to think for myself.
Best wishes
David
Hello Dave,
This is not true I am very interested in the GFT probe. From what I have read it shows compared to the basic Middlebrook and Tian probe differences in the higher frequencies, this is very interesting from the point of view of looking at the (power amplifier) output stage stablity.
In my opinion the output stage causes stabilty problems which are not revealed by the previously mentioned probes but it could just be that the spice models we have access to are not that good.
Is it easy to apply the GFT probe around a basic opamp with feedback, does it show any differences compared to basic probes could you post something.
Regards
Arthur
This is not true I am very interested in the GFT probe. From what I have read it shows compared to the basic Middlebrook and Tian probe differences in the higher frequencies, this is very interesting from the point of view of looking at the (power amplifier) output stage stablity.
In my opinion the output stage causes stabilty problems which are not revealed by the previously mentioned probes but it could just be that the spice models we have access to are not that good.
Is it easy to apply the GFT probe around a basic opamp with feedback, does it show any differences compared to basic probes could you post something.
Regards
Arthur
In all the cases I have checked so far, the differences between the GFT and Tian were small.
Instead, I suspect failures to reveal OPS problems are due to failure to model stray inductance and capacitance, failure to model difficult loads (the 2 uF added to 8 ohms is simplistic), failure to model power supply rail droop ,and similar such incompleteness.
Excellent idea. I will experiment.
Best wishes
David
Hi Arthur
As promised, here are the loop gain plots.
Tz0 is the inner loop.
Tian is the common mode loop. As you can see it's very docile.
Tz1 is the outer loop. As you can also see, I could have a bit better stability if I pushed the outer loop cross-over frequency up even further.
This makes theoretical sense but will scare people.
Me included, so I will have to experiment with this.
I have just found practical transistors for the CMCL so will have to redo this but I believe it's essentially what I will prototype.
Hope this answers some of your questions.
Best wishes
David
Attachments
Hello Dave ,
Thanks for the update, I presume everything was done with the Tian probe.
Looking at the graphs the main poles are at 10kHz-20kHz and the unity gain point of the outer loop at 20MHz and inner loop at 5MHz and 2MHz for the CMCL stage. Well that in part explains the simmed low THD performance at 2ppm 8R@20KHz.
You should build this thing and I am sure it will give you problems that you cannot sim because of the quality of the modeling of the layout and spice device model accuracy. Unfortunetly these problems from my experience can only be solved by having the hardware to play with. I suspect you can make this thing work but you need a very good hardware layout to meet these levels of performance.
Can I ask how may layers you plan to use for your PCB.
Regards
Arthur
Thanks for the update, I presume everything was done with the Tian probe.
Looking at the graphs the main poles are at 10kHz-20kHz and the unity gain point of the outer loop at 20MHz and inner loop at 5MHz and 2MHz for the CMCL stage. Well that in part explains the simmed low THD performance at 2ppm 8R@20KHz.
You should build this thing and I am sure it will give you problems that you cannot sim because of the quality of the modeling of the layout and spice device model accuracy. Unfortunetly these problems from my experience can only be solved by having the hardware to play with. I suspect you can make this thing work but you need a very good hardware layout to meet these levels of performance.
Can I ask how may layers you plan to use for your PCB.
Regards
Arthur
Yes - Tz() is my implementation of an auxiliary Tian probe, so I can look at two loops at the same time.
As you probably know, when you try to improve one loop the other one usually becomes worse and it's nuisance to have to swap back and forth or duplicate circuits.
The main part, I'm sure. The basic amp is reasonably orthodox, there's no secrets, just careful optimisation.
I have modelled some of the layout PCB manually, which is slow and that restricts me to only critical areas. I just hope reality has the same opinion about what is critical.
There must be automated tools to model PCBs, any info appreciated.
So far 2 layer looks like it can meet the requirements.
If I run into problems then I may consider 4 layer, but it seems more complicated than I want to tackle.
Best wishes
David
Perhaps I misunderstand you but I don't think Bob's AES amp has, or needs a CMCL.
The problem arises in combination with the symmetrical IPS.
Best wishes
David
Hi David,
Sorry for the off topic post. How do you implement an auxiliary Tian probe? Can see that this would be a useful thing to be able to do. Do you have an example .asc?
Many thanks
Paul
As I said earlier, off topic isn't an issue here
and probe technique is essentially on topic anyway.I am off to a party now but will post an ASC when I come back.
Not much to it but it is useful.
Best wishes
David
As I said earlier, off topic isn't an issue here
I am off to a party now but will post an ASC when I come back.
Not much to it but it is useful.
Best wishes
David
Thank you David.
Will be very useful to be able to analyse two loops at the same time. Been driving me slowly insane switching between loops.
Enjoy the party.
Paul
If you want to enhance the VAS of the classic Hitachi MOSFET amp[1] http://www.angelfire.com/sd/paulkemble/sound7g.html, you are faced with the choice of enhancing by less than 6dB or else having an indeterminate VAS current.
You have a similar choice when trying to enhance CFA VAS.
Bob gets around it by making the CM for the LTP also regulate CM current.
fig 8 in CordellAudio.com - A MOSFET Power Amplifier with Error Correction
A very simplified version is now my favourite topology but I need to do a lot more work .. eg get to grips with supa dupa probes.
[1] This famous schematic in the Hitachi databook actually hides important secrets that are in the Hitachi commercial amp. The databook circuit, as shown, isn't unconditionally stable with load. Also the commercial circuit regulates the PS to the driver & earlier stages and there are other subtleties. Yes. The excellent performance IS possible with this simple circuit ... but ONLY if you add the secret tweaks.
Cherry Output network
Haven't got time to do serious work on Amps as I've got a lot of microphone & speaker stuff on my plate.
But one thing worth looking at is Cherry's new recommendations for the Zobel/Thiele network.
This Millenium, Prof. Cherry started recommending a simplified Output Network to replace the usual Zobel (10R + 100n) followed by Thiele (L in parallel with 10R).
I can't remember where he says this and would appreciate a reference if anyone digs one up.
I was very dubious initially but it seems at least as good as usual network. For PM & GM, it is neither here nor there .. better (than the usual) for some, slightly worse in others.
Frequency response effects are no worse than the usual too.
Where it really shines is for Unconditional Stability with ANY load. I've always found this the most difficult (real life) test with the usual network. Small (real life) capacitative loads (1-10n) are the most tricky and this correlates well with stability into real life speakers.
And it uses only 3 bits instead of 4
Haven't got time to do serious work on Amps as I've got a lot of microphone & speaker stuff on my plate.
But one thing worth looking at is Cherry's new recommendations for the Zobel/Thiele network.
This Millenium, Prof. Cherry started recommending a simplified Output Network to replace the usual Zobel (10R + 100n) followed by Thiele (L in parallel with 10R).
I can't remember where he says this and would appreciate a reference if anyone digs one up.
I was very dubious initially but it seems at least as good as usual network. For PM & GM, it is neither here nor there .. better (than the usual) for some, slightly worse in others.
Frequency response effects are no worse than the usual too.
Where it really shines is for Unconditional Stability with ANY load. I've always found this the most difficult (real life) test with the usual network. Small (real life) capacitative loads (1-10n) are the most tricky and this correlates well with stability into real life speakers.
And it uses only 3 bits instead of 4
Attachments
Cherry discussed this in Electronics World (a.k.a Wireless World) in July 1997. p 580.
I only have an old photocopy, can't send you an electronic copy.
Best wishes
David
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I read the book first, where he calls it a "differential current mirror", and didn't really take in the description in the article.
To see it as a CMCL is helpful, makes me think more about different types, Thanks.
Best wishes
David
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Du.uuh!
That should be, "Bob gets around it by making the Constant Current Loads for the LTP, also regulate CM current".
Anyone got a link to the CMCL for CFA amps?
_________________
Thanks for this Dave.
Someone sent me a copy but its been languishing unread till now.
IIRC, the one I read was Cherry arguing with another Guru (Self?) this Millenium.
Yes, I noticed that
But I commented a bit hastily the first time, so I wanted to reread the article carefully and include that with any additional discussion.There is a rather supercilious dismissal of Cherry style Zobels in my 2009 edition of Self, but without a reference or even a mention of Cherry's name.
So your recollection would explain that, sounds very believable.
Best wishes
David
No problem, it is simple but it is handy.
Here is a stripped down demonstration.
Iz and Vz are my auxiliary probe and the usual Tian probe has been modified.
The details do not display on the schematic, just to avoid clutter, can be made visible or viewed if you want to see how it works.
Similarly, Vin is switched on and off automatically but I have not made this visible.
I have simplified the example compared to my previous plot that had Tz0() Tz1().
Here there is just Tzan - the Tian loop gain at node Zan - easy to remember
It is most convenient to add the definition of Tzan() to the Plot Defs file.
I have made the modifications so that the definition of Tian in the Plot Defs file does not need to be altered.
Please don't modify the probe without discussion, but use is fine.
I have my own models of the transistors but you can use Bob's.
I have left the details of that to you, depends on where you have put them in your system.
Best wishes
David
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Haven't got time to do serious work on Amps as I've got a lot of microphone & speaker stuff on my plate.
But one thing worth looking at is Cherry's new recommendations for the Zobel/Thiele network.
This Millenium, Prof. Cherry started recommending a simplified Output Network to replace the usual Zobel (10R + 100n) followed by Thiele (L in parallel with 10R).
I can't remember where he says this and would appreciate a reference if anyone digs one up.
I was very dubious initially but it seems at least as good as usual network. For PM & GM, it is neither here nor there .. better (than the usual) for some, slightly worse in others.
Frequency response effects are no worse than the usual too.
Where it really shines is for Unconditional Stability with ANY load. I've always found this the most difficult (real life) test with the usual network. Small (real life) capacitative loads (1-10n) are the most tricky and this correlates well with stability into real life speakers.
And it uses only 3 bits instead of 4
Hello Guru kgrlee
I've given that zobel arrangement a try and so far stability seems just fine with it. I've tried various capacitive loads ranging from 10n to 100n (and higher) and it worked just peachy....And it uses only 3 bits instead of 4
My version of this is similar but uses a few more bits
I drop the resistance across the inductor but put a resistor in series with the Zobel capacitor.
The idea is to have similar overall load on the amp but the inductor better damped.
I also have experimented with a second Zobel in a Pi network, similar to what is discussed in Bob's book.
But I connect this Zobel directly to the OPS transistor emitters rather than after the emitter resistors.
The idea here is to minimize stray inductance so I can push the ULGF up.
At the moment I have 1.8 uH inductor with 2.2 ohms across it, haven't decided on the Pi Zobel values.
Best wishes
David
I believe the extra Zobel(s) at the O/P device emitters is a Cordell favourite.My version of this is similar but uses a few more bits
I drop the resistance across the inductor but put a resistor in series with the Zobel capacitor.
The idea is to have similar overall load on the amp but the inductor better damped.
I also have experimented with a second Zobel in a Pi network, similar to what is discussed in Bob's book.
But I connect this Zobel directly to the OPS transistor emitters rather than after the emitter resistors.
The idea here is to minimize stray inductance so I can push the ULGF up.
At the moment I have 1.8 uH inductor with 2.2 ohms across it, haven't decided on the Pi Zobel values.
I have a lot of 'real life' & theoretical stuff that supports smaller resistors across the Inductor for the 'usual' networks.
There's also RFI which mandates a Zobel AT the speaker terminals but this means its probably too far from the OPS.
However, the PCB may not be the best place for the Thiele (L // R) cos its very close to the huge distorted Class B current tracks.
So the 'usual' networks may be the best in practice after all.
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