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Old 2nd July 2014, 10:26 PM   #1
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Hi Jason. I would like 2+ Symasui please. Do all transistors need to be match?( also those 0.22R resistors).
Quan
Hi Quan,

I think you may have misread the silk screen, there are no 0R22 resistors on the Symasui IPS, but I could see the confusion with R22 being a 22R value. When I put the value on the silk screen it will always be 'inside' the silk pattern for the device, the schematic designator will always be visible when the device is installed.

I would do a basic matching of the TO-92 devices, no need for obsessive pursuits.
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Last edited by jkuetemann; 9th August 2014 at 01:29 AM. Reason: Maintenance
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Old 4th July 2014, 01:56 AM   #2
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Hi Jason, sorry i meant to refer to the OPS trannies and their output resistors 0.22R.
Quan
Ah, I see. No requirement to do any real matching in the OPS. Of course if you have the parts in quantity you could do some selection but it isn't needed. Sorry for the confusion.
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Old 4th July 2014, 02:42 AM   #3
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Originally Posted by jkuetemann View Post
Ah, I see. No requirement to do any real matching in the OPS. Of course if you have the parts in quantity you could do some selection but it isn't needed. Sorry for the confusion.
No problem, thanks.
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Old 14th July 2014, 10:58 PM   #4
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Nice one Jason. Do you have a quick guide to test IPS prior to hooking up to OPS boards. I 've read on the thread about tying FB/VD+/VD- via 470R and testing it this way?.
Quan
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Old 14th July 2014, 11:08 PM   #5
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Resistors can be used to verify the VAS current but the IPS is best tested without them. Just tie the NFB, PD and ND together and measure the output off the NFB point. You will notice with the CFA designs the VAS is heavily loaded by the low impedance FB network and this is less of an issue with the VFA designs. Still, it is nice to be able to run the IPS designs independently.
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Old 15th July 2014, 03:36 AM   #6
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Originally Posted by jkuetemann View Post
Resistors can be used to verify the VAS current but the IPS is best tested without them. Just tie the NFB, PD and ND together and measure the output off the NFB point. You will notice with the CFA designs the VAS is heavily loaded by the low impedance FB network and this is less of an issue with the VFA designs. Still, it is nice to be able to run the IPS designs independently.
Thanks Jason, can you show it on simple diagram ?.
Quan
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Old 16th July 2014, 09:28 AM   #7
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Hi Jason, may be these questions should be over the other thread but does q7 and Q10 on CFA IPS needs to be thermocouple?. How much heat sink do they need?. I can see the space for a flat pierce of aluminum only. I have a couple of small finned heat sink size 2cmX1cmX0.4mm. Would they be ok for those mje 340/350?. TIA.
Quan
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Old 16th July 2014, 01:28 PM   #8
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Quote:
Originally Posted by quan View Post
Hi Jason, may be these questions should be over the other thread but does q7 and Q10 on CFA IPS needs to be thermocouple?. How much heat sink do they need?. I can see the space for a flat pierce of aluminum only. I have a couple of small finned heat sink size 2cmX1cmX0.4mm. Would they be ok for those mje 340/350?. TIA.
Quan
Very minimal heat sinking is required, so a small piece of aluminum sheet is fine. I tested mine without any heat sink at all at +/-45V without any issue.
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Old 18th July 2014, 10:26 PM   #9
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Thanks Jason. I am afraid of not much help to any suggestions. My electronics is pretty basic only high school stuff and my day job is mainly medical. I am learning slowly ,sorry very slow.
Quan
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Old 19th July 2014, 10:12 AM   #10
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Hi Jason, can you check the template for the OPS drilling. I downloaded the v2 but it does not seem to match up properly with the board.
Quan
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