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Old 29th June 2013, 08:54 AM   #1
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Default My New VAS Topology

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Schematic now in LTspice: My New VAS Topology

Hi guys.

In recent years I've been trying to improve on the VAS. Not just modifying existing topologies but I've tried to actually work out a new topology based on the traits I wanted. In short, I've been simulating it for a while now with excellent results. But I've feared taking the plunge and design a PCB and prototype it right off. It would be too risky, something that's not been built and dimensioned before (at least by me). So I decided to actually go ahead and breadboard it and boy I'm glad I did.

The traits I were after were:
-High bandwidth
-Optimal connection to a single ended inputstage's push-pull output
-Active VAS current bias to rid of temperature and device invariances.

The standing current is programmable by a voltage reference (diode, bandgap reference etc) and a sense resistor. A low frequency integrator sets the mirrored conducting current of the input devices. The cool thing is that both the bias process and the actual HF VAS process don't 'see' each other at all; it does not affect THD (simulated).

The schematic isn't overly complex but it's pretty large still. I have to figure out a way to partition it while still making it easy to understand.

The breadboard contains the single ended inputstage (using BF245A as input devices for now), the VAS gain block, bias control and an output buffer follower so I can employ NFB without loading the VAS. All devices are BC550C/BC560C.

I've been running square waves to test and I've been able to optimize it achieving all the traits. The bandwidth is numerous times higher than I achieved with MF80, a basic symmetrical push pull design. There is a roll-off filter of 8MHz.

I've made a few pictures for you to judge, a 1MHz, 200KHz and a 20KHz square wave and a picture of the mad scientist's project The 1MHz square is still full-power.

Thanks for reading if you got this far
Attached Images
File Type: jpg VAS1MHz.jpg (117.4 KB, 1380 views)
File Type: jpg VAS200K.jpg (115.6 KB, 1344 views)
File Type: jpg VAS20K.jpg (120.5 KB, 1314 views)
File Type: jpg VASCircuit.jpg (172.6 KB, 1333 views)
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Last edited by MagicBox; 12th July 2013 at 07:36 PM.
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Old 29th June 2013, 09:17 AM   #2
AndrewT is offline AndrewT  Scotland
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That is phenomenal HF performance for a plugboard prototype !
Is testing to max, hiding overshoot or ringing?
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Old 29th June 2013, 09:24 AM   #3
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excellent , diagram ?
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Old 29th June 2013, 09:45 AM   #4
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Quote:
Originally Posted by AndrewT View Post
That is phenomenal HF performance for a plugboard prototype !
Is testing to max, hiding overshoot or ringing?
Thanks! During building the circuit I learned the finer details of the tuning mechanisms besides the more obvious like Cdom. The circuit has cascoded VAS devices. The following mechanisms I've found:

-Cdom1: Across output cascodes, determines speed of VAS rail.
-Cdom2: Feedback cap across output and VAS input (single ended, inverting input)
-Rfb: Influences, togeter with Cin of inputstage the transfer speed between output and input
-Re1: Degens resistors of input stage, speed of input stage.
-Re2: Degens of VAS input devices, speed of VAS input stage.

By adjusting all of these, trying to tune the speeds of stages so the 'previous' stage is as fast or slightly slower than the stage before, I've been managing to remove over/undershoot as much as I could. I could remove the input filter and it would still be stable but it would show some ringing as it then becomes too fast for the circuit to follow.

It's been quite an adventure pushing and pushing the performance of the circuit. Even the rail litics are needed to retain stability, their effects are clearly visible on the scope, as well as the decoupling elcos across the zener references for the cascodes so their bases can draw the instanious current.
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Old 29th June 2013, 12:25 PM   #5
Bigun is offline Bigun  Canada
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Before you go posting your schematic here - consider if there would be commercial value - a patent or offer it to an audio company.
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Old 29th June 2013, 03:15 PM   #6
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Hi Bigun

I have no idea how to go about that. I had already been prepping the schematic for publication together with the explanation. I don't think my craft is *that* special to warant a patent though but it's a nice thought I'm just excited the schematic works so well. I put it back into the simulator and it still retains its performance inspite of the changes. (Out with mosfets, in with BJTs). It does < 0.0005% THD 200K. I can't get it any better or faster.

In the end though it's the output stage that will slow down the whole thing but with a buffered MOSFET drive, the OPS can be made rather fast too. Too bad I can't hook it up with an output stage and put it to the test
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Old 29th June 2013, 06:13 PM   #7
Zero D is offline Zero D  United Kingdom
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Quote:
Originally Posted by MagicBox

It does < 0.0005% THD 200K
Is that all Amazing

The fact both virtual & actual produce such good performance says a lot.

Be nice to see/hear how it pans out in a completed Amp.

Congrats & All the best.
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Old 30th June 2013, 02:47 AM   #8
AKSA is offline AKSA  Australia
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MB,
I concur with Bigun.
This is VERY fast and there is no indication of instability either.
Consider that when you put it into this forum you CANNOT patent; it is out in the public domain and is no longer your idea.

Formidable!

Hugh
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Old 30th June 2013, 06:38 AM   #9
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Sort of a bummer, I'd love discussing and explaining the schematic for I think there are a few clever things in there that make it all work Now who'd be interested in a schematic? I'm not interested in royalties, just fame and fortune. Oh why not the royalties

I'm a little surprised at all the positive comments, I didn't think my results were that nice. I don't have much to benchmark against except for my previous MF80 symmetrical amp project.
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Old 30th June 2013, 07:10 AM   #10
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Could you use VN88AFD or 2N6658 (Siliconix) as an SE/quasi complementary output buffer...this devices are super fast (>600MHz), highly linear and very, very easy to drive (directly from VAS)?
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