Hi guys,
I'd like to get back (more or less) to the topic of Elvee and his working designs. Here's why. I made a bone head simple emitter follower buffer some time ago. It has some drawbacks (high thd, low damping e.g.) and some obvious pro's. The goal was and is to make a buffer without much of an own character with minimal interaction with the speakers.
I'd like to experiment further with a better buffer and was attracted by Elvee's design. I noticed a few things when simulating and studying the various designs:
- the mosfet design has high thd, but doesn't have drivers for the power mosfets;
- tamimg overshoot and oscillations while retaining a high slew rate is a challenge;
- there are no pcb designs, nor directions how to lay out a pcbs for Elvee's designs.
I want to improve the mosfet design, but with my limited knowledge I need some help. Compare my schematic to the one from Elvee. You can see the changes, which are mostly made for obvious reasons. You need Cordell-Models.txt which I attached.
Let's go step by step and start with obvious flaws which I missed. Do you see any?
I'd like to get back (more or less) to the topic of Elvee and his working designs. Here's why. I made a bone head simple emitter follower buffer some time ago. It has some drawbacks (high thd, low damping e.g.) and some obvious pro's. The goal was and is to make a buffer without much of an own character with minimal interaction with the speakers.
I'd like to experiment further with a better buffer and was attracted by Elvee's design. I noticed a few things when simulating and studying the various designs:
- the mosfet design has high thd, but doesn't have drivers for the power mosfets;
- tamimg overshoot and oscillations while retaining a high slew rate is a challenge;
- there are no pcb designs, nor directions how to lay out a pcbs for Elvee's designs.
I want to improve the mosfet design, but with my limited knowledge I need some help. Compare my schematic to the one from Elvee. You can see the changes, which are mostly made for obvious reasons. You need Cordell-Models.txt which I attached.
Let's go step by step and start with obvious flaws which I missed. Do you see any?
Well Bas, you went from one extreme to the other, and in doing so you took a huge challenge: your initial buffers were rather simple and rustic affairs, but this series of circuits are monsters of performance and also very demanding, since there are no free lunches in engineering.
As if this wasn't enough, you chose one of the simmed-only versions, and you modded it to improve its performance....
You must love difficulty
Here are some first leads: the regular compensation has been disabled and changed to output-referenced shunt, and the gate stoppers have been reduced.
This result in a nice, flat FR response and no oscillations. Of course, everything has to be carefully evaluated, because there might be negative effects.
Regarding construction, it is also quite demanding: I don't use PCB's, I only build on perfboard, and this leaves a lot of room to change something that was overlooked at the initial stage. With PCB's, things are less flexible, and you could end up with a number of tentative versions before arriving at a satisfactory one.
Attachments
Yeah it's from one extreme to the other. This buffer is much more complex and less easy to stabilise. But it offers great advantages at relatively low costs (when compared to the simple design I use now.
About PCB design: from what I understand placement of some components like gatestoppers is critical as are wide and short traces in other places. I'm not to familiar with design rules yet, but most likely they are the same for pcb's and hard wiring or perf board. Thus your builds could offer some nice leads.
I'm making a layout in Eagle at the moment. Let's see what you think of it. I'm probably going to make some obvious mistakes.
I ran some simulations, but I get a massive overshoot and lots of oscillations now. Guess I'm doing something wrong. Can you see what?
By the way. The load is modelled after the speaker it will be driving. However, it should/must be able to drive 4 Ohms with ease. I also intend to use the buffer on Fender cabinets, which sometimes go as low as 2.7 Ohms. As far as I can see, this buffer works with every load you throw at it.
About PCB design: from what I understand placement of some components like gatestoppers is critical as are wide and short traces in other places. I'm not to familiar with design rules yet, but most likely they are the same for pcb's and hard wiring or perf board. Thus your builds could offer some nice leads.
I'm making a layout in Eagle at the moment. Let's see what you think of it. I'm probably going to make some obvious mistakes.
I ran some simulations, but I get a massive overshoot and lots of oscillations now. Guess I'm doing something wrong. Can you see what?
By the way. The load is modelled after the speaker it will be driving. However, it should/must be able to drive 4 Ohms with ease. I also intend to use the buffer on Fender cabinets, which sometimes go as low as 2.7 Ohms. As far as I can see, this buffer works with every load you throw at it.
Attachments
We will try a step by step approach: there are many issues to be addressed as you have discovered, and before you even think of laying-out something physical, all has to be spotlessly clean and well-behaved under any sim scenario you throw at it.
These are difficult topologies, and small signal stability doesn't guarantee stability under all circumstances.
Good point is: once you have successfully tackled all the issues, this buffer is like a rock. It will perfectly drive 0.1 ohm loads if you ask him to (except the transistors will be destroyed in ms, but that's another problem)
These are difficult topologies, and small signal stability doesn't guarantee stability under all circumstances.
Good point is: once you have successfully tackled all the issues, this buffer is like a rock. It will perfectly drive 0.1 ohm loads if you ask him to (except the transistors will be destroyed in ms, but that's another problem)
I second that: one step at the time. Most obviously it's stability that needs to be addressed. I can stop the oscillations, at the cost of 20% overshoot. What is acceptable? I suppose large overshoot can kill the output devices (large currents)...
Next week, I'll have a serious look at the problems; maybe a solution will emerge.
In the mean time, everyone is free to participate and help to the advancement of the subject: I didn't explore this "killer" combination of MOS + drivers so far, and all the ideas from the community are welcome. Such a difficult problem is probably going to need them...
I managed to tame the bipolar version, but the MOS incarnation promises to be more restive, despite their lower transconductance
In the mean time, everyone is free to participate and help to the advancement of the subject: I didn't explore this "killer" combination of MOS + drivers so far, and all the ideas from the community are welcome. Such a difficult problem is probably going to need them...
I managed to tame the bipolar version, but the MOS incarnation promises to be more restive, despite their lower transconductance
I will have a look at the most recent modifications. The only way to test for me is ltspice at the moment, but I can test with a different loads, wave forms, amplitudes, etc.
In the meantime I think about what should be addressed next:
- thermal stability;
- protection against shorted output terminals;
- protection against over voltage;
- coupling to a (tube) VAS or other source;
In the meantime I think about what should be addressed next:
- thermal stability;
- protection against shorted output terminals;
- protection against over voltage;
- coupling to a (tube) VAS or other source;
No difficulty there: you just have to thermally link Q2 with the OP devices; pretty standard stuff.
If you mean protection of the input, protection diodes to the supply rails combined with the input resistor will do the job.
No problem either: for the application you have in mind, the source resistance will be low or even very low, and since this buffer has a decent input impedance, everything should go smoothly.
If there is another source, things could be different, but I don't see for which application you could use it, since it is just a buffer without voltage gain.
That is a much harder problem: designing a protection that is at the same time 100% effective, completely transparent and stable under any circumstance is going to be incredibly difficult.
A more realistic approach would be a latching protection scheme: when some threshold voltage across the source resistors is exceeded, it triggers a SCR-like circuit that disables all the CCS's, and has to be manually reset.
That way, you would avoid a full-frontal confrontation with SOA and loop stability issues.
For better thermal tracking I switched back to a BD139. I read on this forum that a BD139 adapts faster to temperature changes than the transistor I chose.
I meant something different however. If the drivers are mounted on separate heatsinks, the bias resistor will not be able to track them. When the driver temp develops different from the mosfets, bias shift will orrur (correct me if I'm wrong). How to overcome that?
I meant protection of the gate. If I'm not mistaken that's mandatory for Hexfets.
The source I want to use can be DC coupled, no caps involved. The source will consist of the network I use as a load in my schematic followed by a 1k pot. I build the pot with two resistors after the voltage source in my schematics. There must be a faster way to insert a pot in ltspice, but I don't know how. If I put a cap after the voltage source, the DC offset rises. How to correct for that is beyond my knowledge.
For my intended use with a 1k pot: changes of the pot change the high freq response of the buffer (effectively I add more series resistance when turning the pot down/attenuating). DC and THD go up, high freq damping and speed go down. Maybe I see a problem where there isn't one??
I simulated a simple VI limiter which essentially loads the drivers when the voltage over the source resistors rises. It seems we basically had the same idea, implanted differently. When I shorted the output, the current through the mosfets didn't exceed 6 A. Ironically the transistors in the protection circuit had to dissipate several Watts and would probably blow.
Let me elaborate a bit. The driving resistance in the source is 16 Ohms because that is essentially a power soak loading a tube guitar amp. This load is modelled after one of my speaker cabinets and is the same as the network I use as a load for the buffer (the 12.5 ohm res and the following coils and caps).
R15/16 form a 1k pot.
The signal chain is thus as follows (for my intended application): 4/8/16 Ohm reactive load --> 1k pot --> buffer --> 4/8/16 Ohm speaker cabinet.
The buffer is not class A. Idle current can be as low as 80 mA with pretty low THD. The buffer should be well capable of more than 20 Watts also.
It isn't compulsory: IIRC, its presence was justified for some tests, but it could be altered, or scrapped altogether.
That said, going too high with the source impedance will eventually ruin the performances. If the source impedance is really high, an additional layer of buffering is probably necessary: this is a power buffer only.
Initially, these buffers were intended to operate as class AB, and the rest, OP power, source and output impedance are up to the user: they can be designed for any normal context, just like any amplifier.
Rootz decided on some values, that's up to him, I assume he is grown enough to know what he wants: hot class AB seems likely.
A TO126 case can be tied to the main heatsink easily, and is therefore a good choice for thermal compensation, but the BD135 series (including the uselessly high voltage BD139) is not the only one, and other types of cases can be conveniently attached to a heatsink.
That is a common problem for a majority of class AB amps, except for CFP types, where the driver's behavior governs the compound thermal signature.
Many types of answers and solutions are therefore available and readily usable in this case. I recommend you review them, and make an informed choice, knowing that no solution combines all of the ++ without any of the --.
You can use a 15V zener diode between G and S, it will protect the gate in case of (some) mishaps. Ordinarily, big MOS's have a high enough gate capacitance to protect them from handling, etc. They can be destroyed if the in-circuit Vgs reaches unsafe voltages, but if it is the case, they will probably be destroyed anyway, zener or not.
That said, a zener costs nothing, and even if it saves the day in 5% of the cases, it is worth installing.
You should post a schematic, but if you solely rely on the balance of bias currents of the input transistors for a zero offset, you are sure to run into problems.
Source resistance can be a problem, as I said earlier. However, I didn't figure that the 250 ohm of a 1K pot could pose a serious problem.
I'll have to look a little deeper, give me some time.
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If you manage to successfully simulate such a limiter, good for you, but I would expect a more difficult behavior in reality: the handover between the two loops creates a loop in itself, that has to be compensated separately from the two main ones, and this generally results in painful tradeoffs
Personally, I prefer B: no overshoot, no bump in the FR and linearity 0.15ppm against 0.68ppm, but tastes and colors...
With 680 ohm input resistor instead of 330, the figure increases to 0.77ppm, which is still acceptable I think.
A 1K pot would add 250 ohm at most.
Anyway, it is probably not very useful to dissect the sim in fine details : reality will be different.
At this stage, you have to give it a good shake in sim, be sure that nothing breaks loose, latches up or oscillates, even under extreme conditions.
Once you have built a first prototype, you can see where the discrepancies between sim and reality are, try to make them converge, and then only finely optimize the sim.
I'm sorry Elvee, I just spoiled some of your time: I changed the load on the new sim to 8 Ohms to see it's behaviour with a lower reactive load. At the same time I lowered the bias a bit to 80/90 mA (less than 20 W idle dissipation). That explains the higher THD. With the same load and bias level, the THD1 is 0.45 ppm with both sims. THD20 sim is 1.09 ppm for the new sim and 1.24 ppm for the older one. 3rd and 4th harmonics are a bit less. FWIW on a theoretic level (sims) it proves Bob Cordell's statement that with error correction a mosfet OPS can be low THD and efficient, just like BJT's.
The overshoot in the latest sim was at -28/28 V square wave. I should have put it back to -10/10 V to make a fair comparison with the other sim. After doing so, the latest sim showed marginally better damping of oscillations (and a more rounded knee of the square wave). I admit it's probably a moot point and actually building the buffer would reveal it's real potential and flaws.
That brings me to the next questions:
- should the bias q, drivers and mosfets be on the same heatsink?
- When I raise the temperature of the bias q, drivers and mosfets to 50 ºC, the idle current drops to zero. It seems to me that such a drop is to aggressive. Correct me if I'm wrong.
- Should the current sources be thermally coupled?
- Reliable source for Vgs matched IRFP240/IRFP9240?
I'd like to prototype this design. Could take some time however, I'm a bit busy till half Februari. I'd also want to investigate the BJT version more, so I can make an educated choice between mosfet or BJT.
I should have noticed: I wasn't awake enough ...
Opinions differ about this: I have no set mind, it depends on the actual circumstances.
In this case, it is probably too aggressive indeed.
That said, any thermal compensation has to lean on the aggressive side rather than the opposite: losses mean that the effective thermal coupling coefficient will be <1, and due to the transmission delay, a violent power excursion could trigger a thermal runaway if the compensation is tailored to be just sufficient for steady conditions.
A momentary lapse of underbias might be unpleasant, but blown OP devices are even more unpleasant....
In this case, I think that coupling of the Vbe multiplier with the OP devices alone will be just about right. One more thing to confirm with a real prototype
To the OP? No, it would add to the overcompensation
Between them? Nice to have, but not required: tracking will maintain a stasis of the bias conditions, but deviations will be aggressively corrected, and anyway there is no reason the sources should drift far apart (unless you place one of them near a source of heat, which I am sure you won't do)
No idea, they are not supposed to be used in linear applications requiring multiple units, and have therefore no good "official" reason for matching.
Buy a rail or two of each, and match them yourself, this will be cheaper, more reliable, and you will have spare sets in case something goes wrong
Prototyping is probably a necessity: this type of circuit is not especially easy.
It will be interesting to see what the MOS version is capable of: I have only built a bipolar one so far, and its performances seem impressive enough (I haven't been able to confirm the sim results, they are well below my present measurement floor)
Thanks for your answers Elvee. I later realized I made some mistakes when simulating the thermal behaviour of the buffer. The biggest one was that I simulated that all transistors and diodes would rise in temperature to the same extend. This of course isn't true. The diodes in the CCS's probably won't rise 15 °C for example.
So I made a new sim but I still don't seem to fully understand how to simulate and predict thermal behaviour of the mosfet buffer. Here is what I did:
- I fixed all temperatures except for the bias transistor, drivers and output devices;
- I tested three bias transistors: BD139, 2SC3423 and IRF510. They are always on the main heatsink with the output devices;
- I simulated two temperatures for the bias Q, drivers and outputs (25 and 40 °C);
- I simulated with a fixed temperature (separate heatsinks; I assume temperature stays fairly stable when they are on separate heatsinks) for the drivers and with variable temp (when mounted on the main heatsink.
My findings are that with all bias Q's the bias current rises when the drivers are mounted on the main heatsink. This to me seems like a good recipe for thermal runaway.
With the drivers mounted on separate heatsinks and fixed to a temperature of 35 °C (with the assumption their temperature stays pretty stable) and the BD139 or 2SC3423 as bias Q's, the bias still goes up 10 mA with temperature. Only with the IRF510 the bias goes down with temperature if the drivers are mounted on a separate heatsink.
I could thus conclude that I need separate heatsinks for the drivers and should use a mosfet as bias Q, but I'd like to have my findings confirmed. I just don't have the experience with mosfets or triple emitter followers to know from experience what will happen.
Anyhow, I designed a PCB (prototype off course) with the drivers on the main heatsink. That was prior to the most recent simulations. It is however possible to point out some obvious mistakes if there are any.
So I made a new sim but I still don't seem to fully understand how to simulate and predict thermal behaviour of the mosfet buffer. Here is what I did:
- I fixed all temperatures except for the bias transistor, drivers and output devices;
- I tested three bias transistors: BD139, 2SC3423 and IRF510. They are always on the main heatsink with the output devices;
- I simulated two temperatures for the bias Q, drivers and outputs (25 and 40 °C);
- I simulated with a fixed temperature (separate heatsinks; I assume temperature stays fairly stable when they are on separate heatsinks) for the drivers and with variable temp (when mounted on the main heatsink.
My findings are that with all bias Q's the bias current rises when the drivers are mounted on the main heatsink. This to me seems like a good recipe for thermal runaway.
With the drivers mounted on separate heatsinks and fixed to a temperature of 35 °C (with the assumption their temperature stays pretty stable) and the BD139 or 2SC3423 as bias Q's, the bias still goes up 10 mA with temperature. Only with the IRF510 the bias goes down with temperature if the drivers are mounted on a separate heatsink.
I could thus conclude that I need separate heatsinks for the drivers and should use a mosfet as bias Q, but I'd like to have my findings confirmed. I just don't have the experience with mosfets or triple emitter followers to know from experience what will happen.
Anyhow, I designed a PCB (prototype off course) with the drivers on the main heatsink. That was prior to the most recent simulations. It is however possible to point out some obvious mistakes if there are any.
Never mind Elvee, I made a mistake that heavily influenced the results. I simply forgot to make the temp of the bias Q variable and left it fixed instead (not on purpose off course). After I corrected this, the bias behaved as expected: overcompensation! This can be corrected by adding a emitter degeneration resistor or diode (as per Bob Cordell's suggestion; no thermal coupling) to the bias Q which I did. I also tried to further linearise the Vgs multiplier without adding another transistor. As a result bias now drops around 10 mA when going from 25 to 40 °C with the bias Q, drivers and output devices on the same heatsink. This with a 0.4 °C/K heatsink, an idle bias current of 200 mA and +/- 50 V rail in mind. If I'm not mistaken that would mean 16 °C rise of the heatsink at idle around where it would stabilize. Attached is a new sim with the aforementioned Vgs multiplier.
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