Op-amp vs Super TIS
Hi Arthur,
Thank you!
It will be excluded. Not because it isn't discrete, but simply because it has been outperformed by the Super TIS front-end (in terms of complexity, distortion and slew rate). The reason I started to follow the op-amp route, was because a high-end discrete front-end seemed too complicated (see fig.5 on my website, 28 transistors!).
Also the op-amp based front-end, incorporating a NDFL stage, became quite complex, see this one , for example.
On top of that, I still had troubles with the active clamp.
The Super TIS on the other hand, is self-limiting. That means no active clamp and associated circuitry is needed.
So I decided to abandon the op-amp front-end and proceed with the Super TIS.
Cheers,
E.
Hi Arthur,
Thank you!
It will be excluded. Not because it isn't discrete, but simply because it has been outperformed by the Super TIS front-end (in terms of complexity, distortion and slew rate). The reason I started to follow the op-amp route, was because a high-end discrete front-end seemed too complicated (see fig.5 on my website, 28 transistors!).
Also the op-amp based front-end, incorporating a NDFL stage, became quite complex, see this one , for example.
On top of that, I still had troubles with the active clamp.
The Super TIS on the other hand, is self-limiting. That means no active clamp and associated circuitry is needed.
So I decided to abandon the op-amp front-end and proceed with the Super TIS.
Cheers,
E.
Hi Andrew,
Thank you for your kind words.
At he moment, I'm designing an OPS with four pairs of MOSFETs.
As for BJTs, No, see below.
Exactly. That's why I prefer vertical MOSFETs.
HEC doesn't solve the thermal delay issue, of course. But it does decrease the associated distortion, that is, to a certain extent. Anyhow, as always, better avoid than cure'.
Theoretically, that shouldn't make any difference. Practically, I think, it will have some consequences: the more OP trannies, the beefier the driver has to be. It's the latter that might affect the effectiveness of HEC.
Imperfect current sharing has little effect on the distortion, BUT... I'm more afraid of 'current hogging' that might destroy one of the OP devices.
Regarding HEC and OPS bias, I consider it as obsolete (sorry Bob). My auto bias circuit version II not only reduces the distortion (to the same extent as HEC*), but also provides an (high speed) automatic bias control and it doesn't need an elevated front-end PSU. Please look here for a basic implementation.
Disclaimer: No one has built it yet, so I cannot guarantee it really works.
Cheers,
E.
edit; * because it uses essentially the same kind of feed forward frequency compensation.
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hello,
I was thinking of this one:
Distortion Correction Circuits for Audio Amplifiers
J. Audio Eng. Soc., Vol. 29, No. 7/8, 1981 July/August
Fig. 12. Long-tail pair with error correction feedback.
Hello,
I've seen four in parallel in a commercial design.
But I dont remember which brand.
The schematic was published as a discussion in EW/WW
Wow this page really impressed me. In a so concentrated way so exact and DIY friendly explanations, very easy to follow, one can not see "every day". As a matter of fact I didn't see it ever. There's even comparison of TIS to more conventional VAS front-end and politely ruled out simply by the ppm distortion levels.
C o n g r a t u l a t i o n s.
P.S. Will the TIS project be rounded up with a PCB?
PCB
Hi Lazy Cat,
Thank you for your complements! I appreciate your feedback.
>Will the TIS project be rounded up with a PCB?
Maybe. The point is that for a project like this (THD20k ~1ppm), you will need an impeccable PCB, probably comprising four layers. Although I do have a notion of the basic principles, I consider myself not an expert in this field. So I hope someone else feels compelled to design a PCB, that adheres to the requirements for such an amp.
Cheers,
E.
Hi Lazy Cat,
Thank you for your complements! I appreciate your feedback.
>Will the TIS project be rounded up with a PCB?
Maybe. The point is that for a project like this (THD20k ~1ppm), you will need an impeccable PCB, probably comprising four layers. Although I do have a notion of the basic principles, I consider myself not an expert in this field. So I hope someone else feels compelled to design a PCB, that adheres to the requirements for such an amp.
Cheers,
E.
Well, to actually build and verfiy an amp like this on a non-pro DIY-level you'll need a lot of time, experience and access to the finest test equipment available.
So one would need
1) to be a seasoned expert in the field, for the experience part
2) to be retired, to afford the time
3) to have a full-blown lab at hand
Not many people seem to qualify...
Personally I'd find it more appealing to implement a minimalistic version that optimizes performance in relation to parts count and complexity instead of aiming at the ultimate in the sub-ppm realms. Of course the effort Edmond puts into all this, also the well-done documentation, is probably second to none and higly appreciated.
For a managable DIY project, I could think of a working version of the "barebone" approach plus a standard no-frills lateral output and then see how it compares to designs with similar complexity and parts count etc.
So one would need
1) to be a seasoned expert in the field, for the experience part
2) to be retired, to afford the time
3) to have a full-blown lab at hand
Not many people seem to qualify...
Personally I'd find it more appealing to implement a minimalistic version that optimizes performance in relation to parts count and complexity instead of aiming at the ultimate in the sub-ppm realms. Of course the effort Edmond puts into all this, also the well-done documentation, is probably second to none and higly appreciated.
For a managable DIY project, I could think of a working version of the "barebone" approach plus a standard no-frills lateral output and then see how it compares to designs with similar complexity and parts count etc.
I have a question about device selection.
Regarding Figure 2 on your site, at several places (Q2/Q5; Q9/Q11; Q7/Q8; Q16/Q17) I see medium-power driver transistors (KSC3503/KSA1381) where I expect to find small-signal devices. Was this choice driven by the need for large collector breakdown voltages, at the expense of bandwidth (Ft) and output capacitance (Cob)? Or is there another reason for using the TO-126 devices?
Conversely, the output stage uses general-purpose small-signal devices (BC550/BC560) where I expect to see medium-power drivers.
Dale
Regarding Figure 2 on your site, at several places (Q2/Q5; Q9/Q11; Q7/Q8; Q16/Q17) I see medium-power driver transistors (KSC3503/KSA1381) where I expect to find small-signal devices. Was this choice driven by the need for large collector breakdown voltages, at the expense of bandwidth (Ft) and output capacitance (Cob)? Or is there another reason for using the TO-126 devices?
Conversely, the output stage uses general-purpose small-signal devices (BC550/BC560) where I expect to see medium-power drivers.
Dale
Hi Dale,
In fact, KSC3503 & KSA1381 are small signal transistors in a medium-power package, targeted at high definition CRT video output stages. So they do have a high ft and low Cob. Moreover, they have an exceptional high Early voltage. All properties that suit my needs.
Q19 and Q20 are pre-drivers, drawing only a few mA's and operating at a constant Vce of ca. 25V. So in this case BC560 and BC550 are more than adequate.
Cheers,
E.
In fact, KSC3503 & KSA1381 are small signal transistors in a medium-power package, targeted at high definition CRT video output stages. So they do have a high ft and low Cob. Moreover, they have an exceptional high Early voltage. All properties that suit my needs.
Q19 and Q20 are pre-drivers, drawing only a few mA's and operating at a constant Vce of ca. 25V. So in this case BC560 and BC550 are more than adequate.
Cheers,
E.
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Hi KSTR,
And if you find one, most likely, he/she isn't interested in someone else design.
Thank you!
Sure. For a 'super-pmm' amp, you don't need cascodes in the IPS; that save 4 trannies.
The reason a combined the Super TIS with the AB2 OPS is that they are born for each other. Both exhibits low THD and both need a pre-driver*. Another reason is that I get sick of bias stability issues of the OPS. Therefore I opted for an auto bias circuit, which, as a bonus, also provides error feedback. Admittedly, the whole thing is a bit complex, though not as complex as the PGP amp.
But you are right, with laterals you don't need auto bias and the associated complexity. Far more manageable.
Cheers,
E.
edit: * that is, if you want to make TMC effective in reducing OPS distortion.
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LTP
Hi myhrrhleine,
Fig.12 looks the same, but it serves another purpose: error correction.
Thanks, anyhow.
Cheers,
E.
Hi myhrrhleine,
Fig.12 looks the same, but it serves another purpose: error correction.
Thanks, anyhow.
Cheers,
E.
This looks very nice indeed. It fits the instinct that a symmetrical circuit is the natural way to produce a symmetrical response. Or that's my preference and it's nice to see some data to confirm it.
Like KSTR I'm interested in a minimal implementation of this, probably to match a Thermaltrak CFP + EF triple OPS since this is established tech. that I may be able to complete successfully within a human lifetime.
So a few questions.
I would like to minimize the noise since it would be directly connected to compression drivers.
How low can we reduce the feedback resistances? To (partly) compensate the IPS current could be increased. 20mA seems close to optimal for NoiseF if I can still find 2SB737+complements.
The Current Mirror emitter resistors would ideally be increased I think?
What is the benefit of the SallenKey input connection? It can increase the Q of the filter but this only affects the response near cut off, is not a low Q acceptable? To reduce the effective source resistance I am tempted to use an LC filter with a small aircore toroid inductor, any comments?
Finally a very minor observation of a few typos in the web text of the circuit description. In section TMC 'C1 and C17' should be 'C16 and C17'. 'C15 & R25' should be 'C15 & R26'. 'R26 & R27' should be 'R27 & R28'
Thanks for the circuit and the brain workout it has caused me.
David
Like KSTR I'm interested in a minimal implementation of this, probably to match a Thermaltrak CFP + EF triple OPS since this is established tech. that I may be able to complete successfully within a human lifetime.
So a few questions.
I would like to minimize the noise since it would be directly connected to compression drivers.
How low can we reduce the feedback resistances? To (partly) compensate the IPS current could be increased. 20mA seems close to optimal for NoiseF if I can still find 2SB737+complements.
The Current Mirror emitter resistors would ideally be increased I think?
What is the benefit of the SallenKey input connection? It can increase the Q of the filter but this only affects the response near cut off, is not a low Q acceptable? To reduce the effective source resistance I am tempted to use an LC filter with a small aircore toroid inductor, any comments?
Finally a very minor observation of a few typos in the web text of the circuit description. In section TMC 'C1 and C17' should be 'C16 and C17'. 'C15 & R25' should be 'C15 & R26'. 'R26 & R27' should be 'R27 & R28'
Thanks for the circuit and the brain workout it has caused me.
David
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Hi Dave,
Understood that low amp noise is important when driving a high-efficiency compression driver. A power amplifier that achieves input-referred noise of 5 nV/rt Hz is considered very good. Bear in mind that achieving low thermal noise is only helpful if the noise from hum and its harmonics, and rectifier spikes and noise is REALLY kept low.
When trying to achieve low noise, there is no substitute for good noise simulations, as with LTspice, in my opinion. There are often numerous things about circuit noise that may at first be non-intuitive or easily overlooked. If you are new to noise simulation, there is some good easily-digested discussion of noise and its simulation in my book, "Designing Audio Power Amplifiers".
Good luck.
Cheers,
Bob
Thanks, David.
I'm glad we share the same 'instinct'
Well, the noise isn't that much. According my sim 313nV, referred to the input and BW = 10kHz. Perhaps you can lower it to 250nV by means of better trannies and lower impedances. Not really a big deal.
BTW, 20mA is a lot of current for an IPS; trannies will get pretty hot.
Of course you may increase the emitter resistors of the CM's for more mirror accuracy and lower noise, but at the expense of TIS output swing.
This is because you have to increase the bias voltage of the Baxandall trannies (Q13 & Q14) accordingly.
A lower Q is okay.
As long as it doesn't add to distortion (or pickup hum) , it's an acceptable alternative or even better.
Thanks pointing out these typos. I updated the schematic and forgot to update the text as well, hence the errors.
Cheers,
E.
Thanks, I have your book and read it repeatedly! I do find some aspects of circuit noise non-intuitive, like the fact that the current mirror noise decreases as the emitter resistors _increase_. Your circuits values indicate that you know this but it is not mentioned. I know that there's a limit to what you can fit in a book! D. Self also does not mention it but in his case the low values he uses make me wonder if he picked up on this, especially since the overall discussion implies that it's best to minimizes resistances and there is no alert for the trap.
Spice simulation was what alerted me, then I discovered it was already discussed by Samuel Gronner. Still need to _understand_ it better.
As to specifics- 5nV/Hz @ 20X Vin/Vout would still leave about 10dB SPL @1m in the compression drivers. I would like to make it inaudible.
That will take about 2nV/rt Hz. Not easy but should be possible with a 50 ohm source and a 3dB NF.
Best wishes for an even thicker 2nd Edition.
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