Projecting an amplifier with dual input with current mirrors

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hi everybody, this is my first post.

i'm trying to project and simulate this amplifier but something isn't working correctly surely because i'm pretty new in analogue electronics.

i attached the schematic in multisim 12 zipped so everyone can edit and share.

best regards,
Fabio
 

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Your output stage bias circuit is b0rked. You're missing 2 connections after Q13 and Q14.

Speaking of bias circuits, best use one that has the pot between base and emitter of Q15 only. (Then if there is bad contact in the pot, bias can only go down.) R16, R19 seem a bit low maybe?

You don't need 2 pairs of diodes across C3. Just D6 and D8 will do fine - normally there's no more than a few mV on there anyway. Maybe use some that are a bit beefier though, 1N4001/2 or so.
 
the current mirror load for complementary diff pair has a fundamental problem - discussed in several threads

but there are other fundamental topology issues - your "VAS" can't work as shown either


you may have misinterpreted some things if you're working from a published design

ambition is good but you may need to take smaller steps 1st with simpler circuits, we all did
 
first thanks for your replies. jcx you're alright, was better if i started made amplifier from beginning but i wasn't thinking it's so difficult! however i'm not working on a published design, only have seen something in self's book. right now i'm working on the amp, soon i'll post some progress
 
i've improved overall design with some changes and now it amplifies something, now one of the most important problem that i don't know how resolve is the output that is not zero centered. answering to jcx i don't know which kind of problem have the current mirror load for complementary diff pair, but if it can't be resolve i'll change topology. attached are new schematic in pdf and zipped multisim 12
 

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changes

i've changed topology since double current mirrors in input stage seems to have some problems, now i used a double diff input with emitter-follower vas but despite my work the amplifier has a really high distortion. attached pdf and ms12 files. any suggestions are really appreciated :)
 

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If this is a intended as a Blameless style then aren't Q11 and Q12 incorrect polarity?
Shouldn't Q11 be NPN and Q12 be PNP to correct phase in the VAS?
Yes, and D11, D12, D13 and D14 prevent any signal voltage swing at the bases of Q11 and Q12. As it is, Q11 and Q12 just supply a (nearly) constant current to the bases of Q13 and Q14.

Oops, no wait. I just realized the input stage is running off +-15V, so maybe Q11 and Q12 are supposed to be operating as common emitter gain stages.

You could do something like shown below. Q11 and Q12 form a second gain stage with current gain of about 10. Q13 and Q14 form a third gain stage, also with current gain of about 10. If you do this, the "Input" and "NFB" connections to the input stage will have to be swapped because there's now an extra inverting stage.

Hmm, thinks....
OK, that almost works, but now Q2 and Q8 are going to saturate if there's more than about 1V input signal. So we need higher voltage on their collectors, but we don't want higher voltages on the bases of Q11 and Q12. A couple of strategically placed zeners can sort that out. Changing the feedback network to give higher gain would help too.

After the basic design's sorted out, the high frequency compensation's going to need some TLC to ensure stability.

I'll leave it at that for now, since I'm not even sure what direction the OP wanted to go with this design.

edit again: Oops, cross-post with OP. I'll go look at the new version now.
 

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Last edited:
Regarding the circuit in post 9:

There's one fundamental problem there. R2 and R9 are connected to +-13V rails, but R14, R15, R30 and R31 are connected to +-50V rails. That won't work, they have to be connected to the same supply rails. I'd suggest removing R7, R21 and the zeners and running everything off the +-50V rails. (OK, I'd probably drop the supply to +-35V and settle for 50W or so output power, especially with only one pair of output devices. YMMV)

Next problem is the VAS has very low current gain. At the top, it's defined roughly by the ratio of R9 to R30, and at the bottom by the ratio of R2 and R31. So even though you're using Darlingtons, you're only getting a gain of about 10.

I'd work it out as follows:

Current through Q13 and Q14 wants to be at least 10 to 20 mA. Let's say 20 or a bit more. Then R30 and R31 can be redused to 22 ohms each. They still each have about half a volt across them, which should be plenty enough for stability of idling current vs temperature etc.

Now there's going to be about 2V (or a little less?) across each of R2 and R9. If you make them 2.4K each, you get a current gain of about 100 from the VAS. To get the correct voltage drop across them, you need to reduce the input stage idling current, probably to about half, i.e. roughly double R1 and R11.

After that, it's fine tuning. I'd probably reduce R14, R15 and R24 to about 1/3 of their current values, to increase the idling current through Q11, Q12, Q16 and Q17. Output stage bias should be adjusted for about 25mV across each of the emitter resistors (R25 and R26). Adding emitter resistors to Q2, Q3, Q8 and Q9 is probably a good idea too.
 
thx

godfrey you were alright! after implemented these changes the amplifier works almost perfectly i had to add C4 and C10 and reduce C6 to 10pF to remove self-oscillation! now i try some instrumentation on multisim because is the first time i use this program. the output stage i know is under dimensionated but i use only 2 finals for testing purpose, in the final realization the output stage will be 4x 2sc5200 and 4x 2sa1943, and BD139 and BD140 wil be 2sb834y and 2sd880y. i'll post now new schematic and ms12 file and later some measurements.

one last thing i need to know, why resistor in input stage transistor's collectors must be disequal?
 

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...the amplifier works almost perfectly...
Excellent! I assume you checked the voltages and currents all around the circuit to make sure they look reasonable and all the transistors are operating well within their safe limits.
...why resistor in input stage transistor's collectors must be disequal?
I disagree with sgrossklass on this. R3 and R10 actually don't do anything useful, so you can just leave them out. Some designers include them and make them equal to R2 and R9 because .... um.... I dunno - because it makes the circuit diagram look pretty or "balanced" or something?

On a related note; R6, C5 and C7 don't seem to be doing anything useful either, so you could leave them out as well.
...the gain is -3db at 15.9Hz so i think isn't bad :) is the pahse alright?
Actually, there is a slight problem here, which won't show up in the simulator. But first, remember there's no problem getting whatever low frequency response you want. In a circuit like this, there's two low frequency roll-offs: one due to C2 and R5 at the input, and the other due to C3 and R28 in the feedback network. In each case, the roll-off frequency = 1/(2*Pi*R*C).

With your values, the input filter rolls off very low (about 0.03Hz), and C3 + R28 causes the roll-off at 16Hz. The problem is that electrolytic capacitors are quite non-linear, causing distortion, and they really don't like having reverse voltage across them. To minimize the distortion and keep C3 happy, you need to have as little signal voltage across it as possible, which means setting that roll-off to a very low frequency (around 1Hz is normal, but feel free to go lower), and choosing the input cap (C2) to give the desired rolloff.

If you reduce C2 to 1uF, then you can use a plastic cap (without robbing a bank), and still have -3dB at about 8Hz. In the feedback network, I'd increase R27 and R28 ten-fold to 22K and 1K, and maybe increase C3 as well. There's another reason to make R27 the same as R5 (at the input) - it helps to reduce DC offset. In a complementary design like this, it's less important since the base currents of the NPN and PNP input devices will cancel to some extent anyway, but it can't hurt to match those resistors.
...had to add C4 and C10 and reduce C6 to 10pF...to remove self-oscillation...
Hmm... Are you sure it's stable? I'd have expected it to need heavier compensation. To check, you need to do an AC analysis of the loop gain. That is the total gain round the loop from the input to the output, and back through the feedback network to the input.

As you go up in frequency, the loop gain reduces, and the phase shift increases. For stability, the loop gain has to reduce to zero dB before the phase shift reaches 180 degrees.

If there's no fancy tools in your sim to help, the pic below shows one way to do it.
 

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phase analisys

godfrey i checked almost all voltages and currents but whit my understanding i'm not able to judge if everything is correct. now i made the ac analisys on the schematic you've posted and this is the result... i think is there's something wrong since i've never seen a phase plot like this one
 

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