Either your amp is inverting or you've got something wired up wrong.
The "kink" in the phase plot is a wraparound from -180° to +180°. LTspice is smarter here, it can join the curves smoothly.
Looks like you determined closed-loop gain, which is not particularly meaningful. You want open-loop gain.
The "kink" in the phase plot is a wraparound from -180° to +180°. LTspice is smarter here, it can join the curves smoothly.
Looks like you determined closed-loop gain, which is not particularly meaningful. You want open-loop gain.
No, this is exactly what you want to be looking at!
When you measure like this, the phase starts at 180 degrees in the mid-band, and rolls down at high frequencies. So we want gain to drop below zero before phase drops below zero. Ideally, you want a decent amount of phase margin e.g. have phase of say 45 to 90 degrees when loop gain is zero.
On your graph, gain and phase both drop through zero at about 10MHz - not good. It was probably much better before you made the last changes. When you increased R27 and R28, C6 should have been reduced by the same amount to keep things in proportion. Reducing it to 1 or 2 pF should help.
Anyway, let's look at the "Magnitude" graph from your AC analysis and see what's going on. There's three interesting things:
1) Gain starts rolling down above about 40KHz. That's the dominant pole caused by C4, C10 and all the stray capacitance at the output of the VAS.
2) The gain curves upwards above about 400KHz, leveling out somewhat. That's the zero caused by C6. It gives a nice boost to the phase around 1MHz, but that's too soon. Where we need help is around 5 or 10MHz. Hence the suggestion to reduce C6, to move it's effect up in frequency.
3) Above about 10MHz the gain drops fast and phase goes down the plughole. That's pretty much unavoidable, but you need to get the gain down to unity before then.
There's two ways to improve stability:
A) Move the dominant pole down in frequency. The sooner the gain starts rolling off, the sooner it reaches unity.
B) Add zeros to boost the phase at high frequencies. (That's what C6 is trying to do).
It's probably a good idea to experiment a bit, changing one thing at a time to see what effect it has. E.g. compare results with C6=10pF, C6=2pF, and C6=zero.
Another way to boost the phase at high frequencies with a zero is to put a small capacitor (say 22pF to 100pF) between the emitters of Q2 and Q3, and another between the emitters of Q8 and Q9.
If you want to shift the dominant pole down a bit in frequency, you could just increase C4 and C10, but there's another way to do it too. What you have now with C4 and C10 is "shunt compensation". Another way to implement the dominant pole is with "Miller compensation". To do that, leave out C4 and C10, and instead connect a small capacitor between the base of Q12 and the collector of Q14, and another between the base of Q11 and the collector of Q13. I'm guessing here, but I'd say 5 or 10pF should be in the ballpark.
P.S. One thing bothers me a bit about those graphs: the low frequency rolloff below about 10Hz shouldn't be there. It looks like you've somehow got the C2+R5 rolloff included. Or maybe it's just a side effect of whatever you did to get the DC offset to behave.
OK, enough thinking - let's see if I can get to the pub before last round.
have a good time in the pub and drink something also for me i've used the suggested miller compensation and i'm surprised how much it works well! reducing C6 effectively has anticipated the hf rolloff reducing the gain's zero crossing. i tried values from 22pF to 100pF for C5 and C7 like suggested but these values anticipates too much the rolloff in gain's hf range so i opted for 4.7pF, is this a good solution or a value so small can implicate something unwanted?
the analysis of closed loop show a wide bandwidth +-3dB and this make me thinking that maybe i've done a wrong analysis.
however if i'm not in error now the phase margin is about 45 degree and this is good.
like other posts i attach new schematic and ac and open loop analysis.
P.S. god bless internet and forums!
the analysis of closed loop show a wide bandwidth +-3dB and this make me thinking that maybe i've done a wrong analysis.
however if i'm not in error now the phase margin is about 45 degree and this is good.
like other posts i attach new schematic and ac and open loop analysis.
P.S. god bless internet and forums!
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