JFET input, MOSFET VAS, LATERAL output = Perfect!!

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I tried to remember to say that I learned that from KenPeter, but now I remember Paul did it before Ken...

Here is my schematic.

I just realized, it must not help that the source resistor for my MOSFET CCS is only 6R. I will try a different LED model.

No posts were deleted.

- keantoken
 

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Here are some plots from my simulation.

First is AC response and 100KHz phase shift.

Second is output impedance. The dip at 4KHz is caused by the positive rail decoupling caps.

Third is square wave at 100KHz.

Fourth is THD at 1W into 6ohm, 7KHz.

Fifth is the schematic I am simulating.

- keantoken
 

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Oops, I used the wrong input Jfet.

Here are the same tests for the LSK389C. I also remembered how to include slew-rate measurements.

I will explain my modifications to the circuit:

1: I decreased the lag and lead compensations; dunno why I bothered, it doesn't matter much in simulation.

2: I modified the feedback network according to Hugh. Judging by SWF's decision to increase the series feedback resistor to 500R, it would seem Hugh was right. However the question of the feedback shunt remains open.

3: I modified the gate stoppers. I did this with a square wave test, by measuring the voltage between the gates, and adjusting one of the stoppers to cancel the error so that both MOSFETs switch at the same time. This means the PFET will have a smaller stopper to make up for the smaller capacitance. I think Hugh's approach may be opposite to this.

4: The schottkeys used are chosen to have high current, low capacitance, fast recovery. I wonder if SiC schottkeys would work best here? The model I chose seemed to have the best results but the DC characteristics may be much different in the real world.

5: I notice I changed C9 for some reason. Usually from a simulation standpoint, 10nF is enough here from my experience. If not, it's probable that the circuit has stability issues.

6: C10 and V5 are how I test Zout. C10 is zero unless the Zac parameter is changed.

- keantoken
 

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Do you ever test without input filter?
I mean for compensation test with AC analysis.
With filter it will rolloff at 700kHz every time.

Why you have gatestopper at IRF9610 in vas.
This is not needed. The same with emitter resistor to IRF9610. Not needed.

Nice to see you spend so much time with this circuit, keantoken.
There will be people catch up some of your small ideas.
Like the gatestoppers: 360 Ohm vs. 220 Ohm
 
Lineup, you have a good point. I did the square wave test without the input filter. As it turns out, a 75pF miller cap was needed to have good square response. However a 75pF phase lead compensation enables the miller cap to stay at 36pF.

Positive slew rate is indefinite, negative sew rate is -43V/uS.

I don't think overshoot is a bad thing to see on a square wave. Amps seem to sound better with minimal compensation and from what I've seen, some overshoot doesn't mean an unstable amplifier. Actually, the most stable amplifiers in my simulations always showed some imperfection in the square wave, but this was because the devices are being driven outside of their normal conditions by a pulse signal. To adjust compensation to correct for these signals will maladjust the amplifier for signals that are within it's nominal operating range. Erratic/chaotic behavior however, definitely should be looked into. In the end it's easy to test for; just drive the amp into a 470nF cap. Test a range of input impedances for oscillation. And lastly, feed a signal generator into the output through a film cap and watch the output on an oscilloscope for alarming behavior.

I want stop for now and let SWF make the next move. I can aid in various ways on the simulator, but SWF is the one here who can decide which changes sound the best.

- keantoken
 
Thanks keantoken, I will try those diodes as soon as I can get my hands on some. I think you're right about the compensation sounding bad, I notice that the miller cap especially seems to be detrimental. I left it on there to help correct the overshoot but I don't like the sound as much.

Anyway, I have a new problem I'm hoping you guys can help with!

I been hitting the soldering iron prety hard today - made three complete circuits, and I'm back where I started.

I'm still not sure about the rather agricultural 9610 in the VAS, so I am playing around with the ZVP3310A again. It won't have the current to make 200kHz square waves, but I think it will sound better anyway.

Anyway, I'm having a little oscillation problem on the negative half cycle. I'm thinking it might be due to the VAS CCS oscillating. The current circuit is shown below, but I have tried up to 150pF of miller capacitance to no avail. I'd be interested to know what you think might be the cause.

The schematic and oscillogram are below...look forward to your thoughts.
 

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You might try disconnecting C2. Sometimes the input is sensitive, this cap may need more resistance between it and the Jfet gate. But that is not a permanent solution.

Have you tried putting the miller cap on the other side of the gate stopper of the VAS?

I found in simulation, for some reason there was no way I could get the circuit to stop oscillating if I drove it past a certain point. I figured it was a fluke of simulation, and the oscillation doesn't look like what you have.

It appears that the oscillation is associated with higher voltage at the drain of the VAS. This means the drain capacitance is decreasing, increasing the BW of the VAS.

Also, C6/MOSFET and C13 form a positive feedback path for the Jfet. You might try removing the phase lead cap and going from there. I think the right solution here is to put a resistor in series with the phase lead cap to decrease the Q of that feedback path.

Sometimes the double-BJT CCS can cause problems. You may try inserting a 10R+10nF snubber between the emitter and collector of Q2. In simulation this improves the AC characteristics somewhat.

EDIT: Must sleep now. ;)

- keantoken
 
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So far , the following version seems to have by far the best potential,
at least linearity wise.

To not waste gain in the miller compensation , TMC is implemented ,
and this largely improve the VAS+OS global linearity leading to THD
ratios that are as low as 2 ppm at 1khz and about 5 ppm at 10khz
for an output of 10V pk/8 ohm at 0.63A quiescent current.

Harmonics levels distribution is satisfactory as well.

To allow TMC implementation, the VAS gain is enhanced thanks
to an emitter follower preceding the voltage gain stage.

Components added are marginal , 1 transistor , 2 resistors , 1 cap,
while the improvement in linearity is more than an order of magnitude.
 

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