JFET input, MOSFET VAS, LATERAL output = Perfect!!

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OK, WY,

Are you saying:

#1 jfet as per existing design, with bipolar cascode above it.
#2 Cascode device taken resistively to rail.
#3 VAS source taken to non-rail side of cascode load resistor, and gate biased around five volts off the upper rail by a stable voltage reference. VAS output taken off drain, as before.
#4 Fb network unchanged.

This would work of course, and hints of the Lender configuration. But there are problems.

For starters, there will be a phase inversion between input and output of the amplifier, which can be remedied by simply inverting the speaker leads. But the fb will need to be applied to the gate of the input device, rather than its source, and this will change the topology drastically, principally by introducing more phase shift and affecting stability.

Do I read your suggestion correctly?

If yes, would you like to posit a schematic?

Cheers,

Hugh
 
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Hugh,

Thanks for your comments! Don't go changing anything yet because after listening all morning I can definitively say in my opinion this version is not the nicest sounding, unfortunately against all my hopes. It's too clean. I'm sure some people would find it their favourite, as it's the opposite sound to what I have grown to like. I'm about to move in my floor standers to confirm this.

It sounds almost too neutral I think, and bass is disappointing. Unfortunately I was so sure I had the formula nailed this time that I changed quite a few things and I'm not sure exactly what it is that has caused this.

What are your thoughts on the size of my feedback cap and polarizing voltage on the input cap? I suspect one or both of these are the culprit. Btw, my input cap is now 2.2u.

I will try dropping the miller capacitance too.
 
Ah, the nub of the matter.....

Some like it neutral, some like it rich, full bodied. The latter is a distortion which strictly should be eliminated. But if you do eliminate it, and go for neutral (very low THD), you will find many don't like the sound. It's a shame we can't freeze the bank accounts of all these guys and prevent them buying amps, but there it is.....

IMHO there is a connection between musical engagement, whatever that is, and neutral presentation. It seems to me that the more neutral the system, the less is the engagement. It's like rice without sambal. Not sure why, suspect it's the recording process. In any event, you seem to like your rice with sambal, not such a bad thing.

You might like Paul's bootstrap, SWF, it's a nice half way house. But the DN2530s are yet to arrive in the post, yeah, I know. And yes, do reduce that lag compensation (miller cap), I think it's too high. The Miller cap has big influence on the sound.

I think the input cap is not too important; it's set by the gate bias resistor, and 2.2uF is about right. I feel that there should be at least 2V on the gate of the jfet for best input operation. I suspect you could change the fb network resistors to 680/33, with shunt cap of 1000uF. This will give a gain of 21.7, which is 26.7dB, still a bit below the THX standard of 29dB, but close enough for a low power amp.

I count this as a success. You have found a glass ceiling, important step!

Hugh
 
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Hehehe, hugh I was looking forward to us dropping that clever and rather unique ccs on everyone after building a working circuit. It's the nicest and most elegant I have seen. I think it will be the best option, but not having them this weekend I had to build something. Actually on different speakers, this current circuit has its merits.

Btw, turn on tump is more or less inaudible, and always has been with this circuit. I can't hear it over my power switch.

Can't wait for them to arrive! They are special and rare devices.
 
Oh by the way Hugh,

Regarding your comments about the feedback shunt resistor.

Correct me if I'm wrong but increasing this reduces the OLG of the input stage right? You may recall my original circuit with the MOSFET had, i think, 100R in this position, but I dropped it to the current value because I felt thet jfet needed all the help it could get.

Of course this is a minor change and your pcbs can be built to any preferred circuit. Getting this right may have to happen after you and your circle have built and listened.
 
Yes, SWF, the fb shunt resistor in this topology degenerates the input device and reduces OLG, very true. However, degenerating the input device improves its linearity anyways, so to a degree its swings and roundabouts. The topology is so spare however that this resistor also affects closed loop gain with its fixed relationship to the series fb resistor, and by a similar mechanism also affects the bias voltage we must feed the gate to ensure zero output offset. Its crucial significance is the effect on the size of the shunt fb cap, however, and the attendant effect on switch on transients. As you see, all this is an elaborate balancing act. My thoughts are that 33R is about right and we should fiddle other values to make this value work well.....

Hugh
 
Increasing the feedback network impedance in order to use a smaller feedback cap will reduce OLG because the source of the Jfet will see a larger impedance, and lower it's effective transconductance.

Is it possible that a clever bootstrap can lower the load on the feedback cap so a smaller one can be used?

- keantoken
 
Yes, Kean, I think it is possible. Alternatively we could lessen the load on the drain of the jfet by simply replacing the 1K VAS gate/rail resistor with a current source, that would raise OLG at least 6dB.

However, do we need MORE loop gain, or less, in light of SWF's preference for a more 'organic' sound?

I would suggest less..... but, heck, I was wrong once before in 1965!!

Hugh
 
I try not to make any direct suggestions, I just watch for what it is people want to do with the circuit and try to help them get there (although most often my help is not needed)... After all, I have no experience here.

So essentially, guys, I support your decisions, wherever they may go!

By default, I am with Hugh however, just for a failsafe.

I have one rogue idea though. Couldn't we replace all the current sources with bootstraps? After all, who can disagree with a passive current source? It is unlikely to be perfect, but I think it can be tweaked to as good or better performance than an active CCS using a trimmer and AC voltmeter (or scope).

I'll work on a schematic...

- keantoken
 
Kean,

Most of my amps have bootstraps, except one, the Maya, so I tend to agree with you.

However, this is not our design, I defer to SWF who is doing all the heavy lifting and deserves credit, along with the redoubtable Lineout.

You remain the resident 17 year old genius on this forum, nothing can take that from you!

Hugh
 
An LTSpice trick:

If you include this line:

.four {Freq} V(Vout)
.four {Freq} 4 V(Vout)

LTSpice will calculate the total THD twice: once computing all the harmonics, and secondly computing only the first 4 harmonics. The second number can be divided by the first to check for Hugh's 98% criteria. Note that if your circuit's noise floor is above the 4th harmonic, the distortion number will be wrong. A low noise floor is mandatory, so I recommend making the feedback and input caps 1 farad in simulation and this will correct most of the drift.

BTW, I have my simulation of this circuit ready.

Thanks for the compliment Hugh.

- keantoken
 
Hugh,

I managed to get some of the magic back. It's sounding quite good now. I upped the series feedback resistor to 500R again. I'm not sure if it is the reduced feedback or the extra voltage it requres across the input cap, but it sounds much better this way.

By the way, I was looking at the F5 schematic and I see Nelson Pass used 10R shunt resistors for the jfets - maybe 20R is on the money?
 
If you want to lower the shunt feedback resistor substantially then I think you will want to worry more about the capacitor's parasitics and behavior. I wouldn't suggest going under 10R because the capacitor's self-resonance might become more pronounced. Why not try paralleling the cap with a 100n+10R snubber, so the HF impedance is less ambiguous? I think it is good practice to keep resistances larger than component inductances; this keeps reactivity and resonance reasonable and managed.

- keantoken
 
In the schematic attached the figure is over 99.9%, as long as you don't go over say 3A output. The output bias current affects this figure strongly; higher bias current decreases high order harmonics. Go to the miller cap and plot it's current. Now right click on the trace's name and enclose the label with D(). This will show you in a very visual and effective way the distortion which is causing this. I will try adding schottkeys to the MOSFET sources to see if I can increase non-switching behavior.

Mikelm, I defer to your wisdom since you know from experience.

PS, SWF, if you look at the current through the 20R VAS degen and the drain current of the CCS, I think you will find that most of the VAS current is consumed by the CCS, not the output transistors. I think using the BJT/MOSFET CCS would help to a great degree.

- keantoken
 
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