Hello all,
Please be gentle, my electronic knowledge is barely above high school level
Having built a pass clone and JLH I'm now trying to build a simple 2 stage mosfet class A amplifier of my own design. It will hopefully have a source follower output stage and a buffering and voltage amplifying input stage (common source). And for the fun of it I am trying to avoid global feedback, but I will add it if necessary.
This is my first attempt at designing anything myself and I have blatantly stolen Nelson Pass' Zen amplifier current source so I'm not claiming to be original.
I am trying to model the thing in LTSpice and you can see the model attached. Please note that the irf510s will not be used in practice - I will try to find something more suited to the job. These were all I could find in the standard LT spice parts library. Also the resistors on the input will be pots for adjustment of the operating point.
Anyway, I guess the first thing to ask is can you spot anything that is a glaring omission or circuit shortfall? Is this project worth following through or am I wasting my time?
Now for my main question. The problem I am having is that because the input fet is current sourced it has an extremely high gain and I get full voltage swing with only a few tenths of a volt input. Is there anything I can do to get around this, apart from add an impractically large source resistor, or is this just never going to work?
Any advice regarding the circuit design in general would be appreciated.
Greg.
Please be gentle, my electronic knowledge is barely above high school level
Having built a pass clone and JLH I'm now trying to build a simple 2 stage mosfet class A amplifier of my own design. It will hopefully have a source follower output stage and a buffering and voltage amplifying input stage (common source). And for the fun of it I am trying to avoid global feedback, but I will add it if necessary.
This is my first attempt at designing anything myself and I have blatantly stolen Nelson Pass' Zen amplifier current source so I'm not claiming to be original.
I am trying to model the thing in LTSpice and you can see the model attached. Please note that the irf510s will not be used in practice - I will try to find something more suited to the job. These were all I could find in the standard LT spice parts library. Also the resistors on the input will be pots for adjustment of the operating point.
Anyway, I guess the first thing to ask is can you spot anything that is a glaring omission or circuit shortfall? Is this project worth following through or am I wasting my time?
Now for my main question. The problem I am having is that because the input fet is current sourced it has an extremely high gain and I get full voltage swing with only a few tenths of a volt input. Is there anything I can do to get around this, apart from add an impractically large source resistor, or is this just never going to work?
Any advice regarding the circuit design in general would be appreciated.
Greg.
Attachments
From your drawing, I'm assuming you're running this from a single rail of 56 Volts.
This means you're expecting to get a peak output voltage of something around 24 Volts.
Across an 8R load tht's a peak current of 3 Amps.
As it's not pushpull but fed from a current source then your standing current is also 3 Amps.
This means your total dissipation between the two output devices is 168 Watts.
Are the devices capable of this?, and you're going to have to have lots of heat sinking. Also you are going to have to make sure the output is stable at half the rail volts otherwise one output device will be dissipating rather more power......early demise....
Regards
Henry
This means you're expecting to get a peak output voltage of something around 24 Volts.
Across an 8R load tht's a peak current of 3 Amps.
As it's not pushpull but fed from a current source then your standing current is also 3 Amps.
This means your total dissipation between the two output devices is 168 Watts.
Are the devices capable of this?, and you're going to have to have lots of heat sinking. Also you are going to have to make sure the output is stable at half the rail volts otherwise one output device will be dissipating rather more power......early demise....
Regards
Henry
Thanks Henry.
You're quite correct in your interpretation. The schematic is a proof of concept. I intend to use multiple output fets in parallel and drop the quiescent current through each one to an amp or so. The fets will be paralleled as per the Aleph design and the source sense resistor will be increased accordingly. In any case output current and PS voltage need some tweaking for the final design. I'm just trying to get the concept sorted.
Any suggestions regarding keeping the output stable at 1/2 the supply voltage? I had rather hoped adjusting the bias pot at the input would be sufficient.
You're quite correct in your interpretation. The schematic is a proof of concept. I intend to use multiple output fets in parallel and drop the quiescent current through each one to an amp or so. The fets will be paralleled as per the Aleph design and the source sense resistor will be increased accordingly. In any case output current and PS voltage need some tweaking for the final design. I'm just trying to get the concept sorted.
Any suggestions regarding keeping the output stable at 1/2 the supply voltage? I had rather hoped adjusting the bias pot at the input would be sufficient.
Any suggestions on how I might implement this?
The attached image is more what I was intending for the output stage to handle the 56v V+. Guess I should have posted a full schematic initially. I wasn't concerned with that part of the circuit.
Attachments
Hmmmm, now you're asking, Lol.
First you need to have some idea of the correct bias voltage for the input Fet. Then take a resistive voltage divider from the output to ground to give you a similar voltage to bias. Include a trimmer in the ground end to adjust the divided output. Decouple your divide volts with a suitable cap, say 220uF, then feed this via a 47K resistor to the input Fet gate.
First you need to have some idea of the correct bias voltage for the input Fet. Then take a resistive voltage divider from the output to ground to give you a similar voltage to bias. Include a trimmer in the ground end to adjust the divided output. Decouple your divide volts with a suitable cap, say 220uF, then feed this via a 47K resistor to the input Fet gate.
I think you should disconnect the input from the bias string R3/4.
Connect the input to the bias string via a large value resistor.
Decouple the bias voltage to signal ground.
1k0 for output gate stoppers is unusually high.
Do you realise that if you return the speaker to V1 you get a constant current draw on your power supply?
If M2 as a CCS load gives too high first stage gain then consider replacing it with a resistor load. And to further reduce the gain (if still lower is needed) increase the degeneration resistor.
Connect the input to the bias string via a large value resistor.
Decouple the bias voltage to signal ground.
1k0 for output gate stoppers is unusually high.
Do you realise that if you return the speaker to V1 you get a constant current draw on your power supply?
If M2 as a CCS load gives too high first stage gain then consider replacing it with a resistor load. And to further reduce the gain (if still lower is needed) increase the degeneration resistor.
Ha, amazing. I thought this would be far too simple a solution but I modelled it and it works perfectly. Thanks for such an elegant solution. It allows me to pretty much remove the bias controls from the front of the amplifier too (see revised circuit). Any other suggestions Henry?
Attachments
1) I'm guessing the bias decoupling is no longer needed with revised version (see above post)? Got a lot of resistance between the bias source and the input now.
2) Yes, you're right about the gate stoppers. Dropped them to 221R now.
3) The idea to connect the speaker to v+ was a revelation. Thank you. Power supply will thank you too.
4) I'm hoping if I switch to a fet with lower transconductance things will improve somewhat. Trying a few things before I abandon the CCS idea.
Thanks,
Greg.
I'd reduce the values of R5 and R17 to a much lower value so C7 gets to it's operating voltage much sooner, 2k/680R would be fine.
Can't see there's any advantage to connecting your speaker to the supply, you just end up with 56 volts DC on your speaker - an accident waiting to happen.
If you don't mind the speaker floating above ground then you could coonect it to the output and then to two big caps, one to supply and one to ground. That would lessen the amount of switch-on thump.
Regards
Henry
Can't see there's any advantage to connecting your speaker to the supply, you just end up with 56 volts DC on your speaker - an accident waiting to happen.
If you don't mind the speaker floating above ground then you could coonect it to the output and then to two big caps, one to supply and one to ground. That would lessen the amount of switch-on thump.
Regards
Henry
Almost there
OK Thanks Henry, done.
I've now replaced the input fets for more realistic ZVN3310s (which I was able to get a manufacturer spice model for), and tweaked the resistor values. Think I've got it about as good as I'm going to for now. Attached is the semi final circuit and a simulated output with 2.2v P-P input. This is just before clipping which begins in the input stage first due to it being biased 4v or so higher than the output stage. I think a 40V P-P output is a good start (see attached).
I may up the input source resistor a little more, but I think clip onset at an input of 2.2v p-p is probably satisfactory.
Now to order some parts...
OK Thanks Henry, done.
I've now replaced the input fets for more realistic ZVN3310s (which I was able to get a manufacturer spice model for), and tweaked the resistor values. Think I've got it about as good as I'm going to for now. Attached is the semi final circuit and a simulated output with 2.2v P-P input. This is just before clipping which begins in the input stage first due to it being biased 4v or so higher than the output stage. I think a 40V P-P output is a good start (see attached).
I may up the input source resistor a little more, but I think clip onset at an input of 2.2v p-p is probably satisfactory.
Now to order some parts...
Attachments
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the speaker does not care whether it is capacitor coupled from half rail voltage to zero volts or from half rail voltage to V1 volts.
The big difference comes from the effect that moving, the speaker from parallel to the CCS, to parallel to active half of the amplifier, has on the way the power supply has to supply current.
Look at the two main routes fro current from V+ to zero volts.
The first stage is a CCS feeding the input stage.
The second stage is a CCS sinking current from the second stage amplifier.
When the speaker is moved to V+ you now have two stages each with a CCS. That gives the supply a constant current load.
This is one of the very few ClassA topologies that is truly constant current.
I have never built a SE power amplifier, but I think moving the speaker V+ is an experiment that may turn out to be very good.
First, thank you both for your help along the way. I'm glad to have it near a final state.
In simulation AndrewT's comments are absolutely correct.
I can see how AndrewT's methods would make life easier on the power supply and allow a simpler design, especially if you were to use a regulated supply. Will definitely have to try it.
Going shopping for some parts today.
I have high hopes for this amplifier and think it has the potential to sound quite good I
Again, thanks to the both of you.
Greg.
In simulation AndrewT's comments are absolutely correct.
I can see how AndrewT's methods would make life easier on the power supply and allow a simpler design, especially if you were to use a regulated supply. Will definitely have to try it.
Going shopping for some parts today.
I have high hopes for this amplifier and think it has the potential to sound quite good
IAgain, thanks to the both of you.
Greg.
Hmm,
I've gone back to this design as I have it sounding quite nice now. Dropped the source resistor of the input fet to 200R which gave me more gain. Also increased Iq to 2 amps per fet (30V rail voltage). Sounds good.
The problem I have now is that because the input stage is current sourced, its gain is essentially dependent on the transconductance of the input fet.
This works well for a single channel, but as no two fets are exactly the same how will I make two channels have the same gain? Is there any way of doing it without removing the current source entirely and using a drain resistor? Or perhaps that is the only way? Anyway, would love some advice on this.
I like the idea of the current source, but I need to have a set and known gain so I can have a matched pair of amps.
Look forward to your suggestions!
Cheers,
Greg.
I've gone back to this design as I have it sounding quite nice now. Dropped the source resistor of the input fet to 200R which gave me more gain. Also increased Iq to 2 amps per fet (30V rail voltage). Sounds good.
The problem I have now is that because the input stage is current sourced, its gain is essentially dependent on the transconductance of the input fet.
This works well for a single channel, but as no two fets are exactly the same how will I make two channels have the same gain? Is there any way of doing it without removing the current source entirely and using a drain resistor? Or perhaps that is the only way? Anyway, would love some advice on this.
I like the idea of the current source, but I need to have a set and known gain so I can have a matched pair of amps.
Look forward to your suggestions!
Cheers,
Greg.
U1 is the CCS, U2 is the amplifier.
set up U1 such that variations in it's parameters do not (significantly) affect it's CCS performance.
You can add a trimmer to the 62r to set the current exactly. Current is now independent of the FET parameters. You could choose two FETs, one for either channel, that have similar Vgs at their operational Id (CCS current).
The amplifier "gain" should not be significantly dependent on the U2 FET parameters. The resistors around the device set the currents and the gains such that their influence swamps variations in FET parameters with regard to stage gain.
Again selecting two FETs (one for each channel) with similar Vgs at operational Id will bring the FET performance closer together. But here the FET operates over a range of currents as the stage passes signal.
It would be better if you could choose two FETs that closely match in ID for a range of Vgs values. Doing this manually is a laborious job and may not return any audible benefit.
set up U1 such that variations in it's parameters do not (significantly) affect it's CCS performance.
You can add a trimmer to the 62r to set the current exactly. Current is now independent of the FET parameters. You could choose two FETs, one for either channel, that have similar Vgs at their operational Id (CCS current).
The amplifier "gain" should not be significantly dependent on the U2 FET parameters. The resistors around the device set the currents and the gains such that their influence swamps variations in FET parameters with regard to stage gain.
Again selecting two FETs (one for each channel) with similar Vgs at operational Id will bring the FET performance closer together. But here the FET operates over a range of currents as the stage passes signal.
It would be better if you could choose two FETs that closely match in ID for a range of Vgs values. Doing this manually is a laborious job and may not return any audible benefit.
Thanks Andrew,
So if I understand you correctly, what you are saying is this:
If the current source can be matched for both channels (ie, flow exactly the same current), the gain of the input fets will also be identical, or at least very similar.
This is done by using a trimmer for the current sense resistor to make sure both current sources flow the same current. Have I understood you correctly?
I can see that in a way this is like having identical drain resistors which, if the source resistors are also matched, would make the gain identical.
The only thing that confuses me is that the current source has essentially infinite impedance, which means the gain of the amplifier fet, theoretically, is infinity/Rs. As a gain of infinity is impossible the gain becomes limited by the transconductance of the amplifier fet, which is different for all fets, even if I match Vgs.
So are you suggesting I should just match the amplifier fets as best I can and accept uneven gain between channels, or will trimming the ccs even things out? (hope this makes sense).
I guess one thing I could do is make the amplifier Rs adjustable and then trim the gain of both channels with an input source of known voltage. Thoughts?
Thanks for your help.
So if I understand you correctly, what you are saying is this:
If the current source can be matched for both channels (ie, flow exactly the same current), the gain of the input fets will also be identical, or at least very similar.
This is done by using a trimmer for the current sense resistor to make sure both current sources flow the same current. Have I understood you correctly?
I can see that in a way this is like having identical drain resistors which, if the source resistors are also matched, would make the gain identical.
The only thing that confuses me is that the current source has essentially infinite impedance, which means the gain of the amplifier fet, theoretically, is infinity/Rs. As a gain of infinity is impossible the gain becomes limited by the transconductance of the amplifier fet, which is different for all fets, even if I match Vgs.
So are you suggesting I should just match the amplifier fets as best I can and accept uneven gain between channels, or will trimming the ccs even things out? (hope this makes sense).
I guess one thing I could do is make the amplifier Rs adjustable and then trim the gain of both channels with an input source of known voltage. Thoughts?
Thanks for your help.
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