Hi gerenis69,
The distortion may have been swamped by the effects of imperfectly matched input transistors. You cannot match these parts using the beta function on a meter, nor by measuring the E-B voltage drops (ineffective method).
To match a pair of transistors (you use two pairs in the CFP arrangement), it is imperative that the parts must be at the same temperature. There is a jig in use by some members of this web site that does exactly that. You measure the voltage difference between the collectors of a diff pair in the test jig. This method does work and results in reduced distortion in most amplifiers. The bad amplifiers have too many other problems to tell.
The design of this jig was detailed in one of the Adcom GFA565 threads, and some members are selling PCBs for it. I have checked one and it works as it should.
So if you are going for the lowest distortion in your design, you must start with very closely matched pairs. These pairs are so closely matched that you must do the same with the degeneration resistors or you will throw the match off. You can sort to within 1/2% or less, depending on how many parts you are willing to test.
-Chris
The distortion may have been swamped by the effects of imperfectly matched input transistors. You cannot match these parts using the beta function on a meter, nor by measuring the E-B voltage drops (ineffective method).
To match a pair of transistors (you use two pairs in the CFP arrangement), it is imperative that the parts must be at the same temperature. There is a jig in use by some members of this web site that does exactly that. You measure the voltage difference between the collectors of a diff pair in the test jig. This method does work and results in reduced distortion in most amplifiers. The bad amplifiers have too many other problems to tell.
The design of this jig was detailed in one of the Adcom GFA565 threads, and some members are selling PCBs for it. I have checked one and it works as it should.
So if you are going for the lowest distortion in your design, you must start with very closely matched pairs. These pairs are so closely matched that you must do the same with the degeneration resistors or you will throw the match off. You can sort to within 1/2% or less, depending on how many parts you are willing to test.
-Chris
For a BJT LTP, output current is dependent upon Ib. That is, it will function as an LTP in as much as source impedance allows Ib to change in response to input voltage.
Say you have an LTP biased at 5mA per transistor and each transistor has Hfe of 500. The total emitter resistance will be 10.8 ohms. So 1mV input generates 93uA output current. With an Hfe of 500, this results in 186nA of input current. 1mV/186nA=5.38k. Your LTP has an input resistance of about 5.38k.
So now we know that if we use a 5.38k source impedance, input voltage will be halved, and so transconductance will be effectively halved as well.
Since OLG is proportional to the transconductance of the input pair, OLG will also be halved. Since THD is open loop distortion divided by OLG, THD will then be doubled.
As a rule of thumb, Zin<<0.054/Iq*Hfe which is the point where source resistance causes THD to double.
A 25k pot has 6.25k impedance at half volume, so it is reasonable to expect double THD at half volume for BJT input amplifiers when using a 25k pot.
Say you have an LTP biased at 5mA per transistor and each transistor has Hfe of 500. The total emitter resistance will be 10.8 ohms. So 1mV input generates 93uA output current. With an Hfe of 500, this results in 186nA of input current. 1mV/186nA=5.38k. Your LTP has an input resistance of about 5.38k.
So now we know that if we use a 5.38k source impedance, input voltage will be halved, and so transconductance will be effectively halved as well.
Since OLG is proportional to the transconductance of the input pair, OLG will also be halved. Since THD is open loop distortion divided by OLG, THD will then be doubled.
As a rule of thumb, Zin<<0.054/Iq*Hfe which is the point where source resistance causes THD to double.
A 25k pot has 6.25k impedance at half volume, so it is reasonable to expect double THD at half volume for BJT input amplifiers when using a 25k pot.
I believe Self talks about non-linear input capacitance to the substrate/supplies rather than the exponential Ib/Vbe. The input cap is nonlinear versus voltage, and thus causes distortion with appreciable input R.
He also gives a solution: bootstrapping the supplies will swing the input cap 'far side' with the signal so will keep the voltage across it constant. Works best with gain of one stages of course.
Jan
He also gives a solution: bootstrapping the supplies will swing the input cap 'far side' with the signal so will keep the voltage across it constant. Works best with gain of one stages of course.
Jan
Sure but my test circuit shows a 5dB drop in loop gain going from 1 ohm source R to 10k source.
The question is which is the greater source of distortion with a rising input Z. The 5dB loop gain drop, the early voltage effect or a mismatch of input Z at the two input terminals? A input diff stage seems far more sensitive to balance than gain.
The answer only addressed one source. I don't think it's the dominate one.
The question is which is the greater source of distortion with a rising input Z. The 5dB loop gain drop, the early voltage effect or a mismatch of input Z at the two input terminals? A input diff stage seems far more sensitive to balance than gain.
The answer only addressed one source. I don't think it's the dominate one.
I have done several simulations and cannot seem to duplicate Self's results. This does not mean that they are not real, since SPICE does not always model accurately subtle effects of real-world transistor shortcomings. However, good circuits are designed to be less sensitive to transistor shortcomings.
In his 7-page discussion, Self seems to imply some plausible reason for the poorer PSRR with the higher source impedance, but really does not put forward a plausible reason for the increased distortion - at least not one that I could find in those 7 pages.
There is, however, a cardinal sin that is committed in the design of the circuit which he refers to as giving him this trouble - at least in my opinion. Using the bias voltage generated in the VAS load feedback current source to bias the input tail current source is just asking for trouble. First, it destroys the high output impedance of the tail current source that would otherwise exist. This alone would seem to explain the poor PSRR.
However, it gets worse than this. The shared biasing sets up a feedback path from what's going on in the VAS back to the input stage, via the tail current source. The feedback transistor in the VAS load feedback current source does its best to keep the VAS current constant, despite voltage swings at the VAS collector that change the VAS current source's transistor beta via Early effect and also reacts to nonlinear current fed back from the VAS current source collector via the nonlinear Ccb of that transistor. This may somehow be playing a role in creating the increase in distortion when the source impedance is higher, especially at high frequencies. Although he briefly speculated about using a separate negative feedback current source for the tail current source, it does not appear that he tried this to see if it would kill both problems.
While on the subject of PSRR of the input stage, it is worth pointing out that the simple 2T current mirror used to load the input stage does not provide as much common-mode rejection as desired. That current source with a helper transistor (EF buffering the pair of bases) provides a good 20dB more common mode rejection. This means that tail current source current fluctuations will produce much less net current out of the current mirror into the VAS. The extra Vbe of headroom for the current mirror input transistor helps keep it further away from any quasi-saturation effects as well.
Not being able to duplicate these results to any significant degree in SPICE, even at 20kHz, seems to suggest that the problem is not collector-base capacitance nonlinearity in the input transistors, nor does it seem to suggest that it is beta nonlinearity in those transistors.
In his circuit, BTW, there is a total of 200 ohms of degeneration in the emitter circuit of the LTP. If beta were 100, this would mean that the open-loop differential input impedance of the LTP would be on the order of 20k. This against a 1k source impedance would decrease loop gain by less than 1dB.
I don't know the answer, but I would put my money on the very ill-advised sharing of the input and VAS current sources as playing a role in these problems. All to save what probably amounts to 1 transistor and one resistor. This is NOT clever, and is not something I would ever, ever do in an amplifier design.
Cheers,
Bob
In his 7-page discussion, Self seems to imply some plausible reason for the poorer PSRR with the higher source impedance, but really does not put forward a plausible reason for the increased distortion - at least not one that I could find in those 7 pages.
There is, however, a cardinal sin that is committed in the design of the circuit which he refers to as giving him this trouble - at least in my opinion. Using the bias voltage generated in the VAS load feedback current source to bias the input tail current source is just asking for trouble. First, it destroys the high output impedance of the tail current source that would otherwise exist. This alone would seem to explain the poor PSRR.
However, it gets worse than this. The shared biasing sets up a feedback path from what's going on in the VAS back to the input stage, via the tail current source. The feedback transistor in the VAS load feedback current source does its best to keep the VAS current constant, despite voltage swings at the VAS collector that change the VAS current source's transistor beta via Early effect and also reacts to nonlinear current fed back from the VAS current source collector via the nonlinear Ccb of that transistor. This may somehow be playing a role in creating the increase in distortion when the source impedance is higher, especially at high frequencies. Although he briefly speculated about using a separate negative feedback current source for the tail current source, it does not appear that he tried this to see if it would kill both problems.
While on the subject of PSRR of the input stage, it is worth pointing out that the simple 2T current mirror used to load the input stage does not provide as much common-mode rejection as desired. That current source with a helper transistor (EF buffering the pair of bases) provides a good 20dB more common mode rejection. This means that tail current source current fluctuations will produce much less net current out of the current mirror into the VAS. The extra Vbe of headroom for the current mirror input transistor helps keep it further away from any quasi-saturation effects as well.
Not being able to duplicate these results to any significant degree in SPICE, even at 20kHz, seems to suggest that the problem is not collector-base capacitance nonlinearity in the input transistors, nor does it seem to suggest that it is beta nonlinearity in those transistors.
In his circuit, BTW, there is a total of 200 ohms of degeneration in the emitter circuit of the LTP. If beta were 100, this would mean that the open-loop differential input impedance of the LTP would be on the order of 20k. This against a 1k source impedance would decrease loop gain by less than 1dB.
I don't know the answer, but I would put my money on the very ill-advised sharing of the input and VAS current sources as playing a role in these problems. All to save what probably amounts to 1 transistor and one resistor. This is NOT clever, and is not something I would ever, ever do in an amplifier design.
Cheers,
Bob
I simulated three amps I have built.
1. Classic blameless with BJT LTP and CM. Increase in input distortion with source output resistance was major distortion source, much higher than the amp distortion with zero source output resistance.
2. FET LTP bootstrap cascoded with CM. Very similar to first case. That one surprised me, I expected much lower input distortion??
3. My CFA with complementary BJT input. Input distortion was much less influenced by the source output resistance and was quite low, probably reason, some cancelation of the input base currents.
Damir
1. Classic blameless with BJT LTP and CM. Increase in input distortion with source output resistance was major distortion source, much higher than the amp distortion with zero source output resistance.
2. FET LTP bootstrap cascoded with CM. Very similar to first case. That one surprised me, I expected much lower input distortion??
3. My CFA with complementary BJT input. Input distortion was much less influenced by the source output resistance and was quite low, probably reason, some cancelation of the input base currents.
Damir
Yes, they were done large signal, not far from clipping, at both 1kHz and 20kHz, into an 8-ohm load.
The design used a degenerated LTP with 2mA tail current provided by an independent feedback current source. 220-ohm emitter resistors were used, providing 10:1 degeneration. The IPS load was a simple 2T current mirror, also with 220-ohm degeneration resistors. A conventional 2T VAS was used, biased at 10mA with an independent 10mA feedback current source. The output stage was a double EF. Miller compensation set the ULGF at a conservative 500kHz. Rails were 35V. The simulation was run at 50W. The feedback network was 1k and 19k, for a gain of 20. In the tests for the phenomenon, simulations were also run with a very low impedance FB network of 100 ohms and 1.9k with little difference.
The simulation experiment was also run with the shared-bias feedback current sources used by Self. However, this also did not provide verification of the phenomenon. It was clear, however, that the connection caused a small amount of signal current to appear in the tail current source current as a result of feedback from the VAS creating the bias voltage for the tail current transistor.
Using the shared bias connection for the current source, THD-20 was 0.00804% and 0.00787% for source impedances of 1 ohm and 1k, respectively (yes, distortion actually went down a hair with the 1k source impedance). THD-1 numbers were 0.000395% and 0.000404%, respectively. Going all the way to a 10k source impedance did increase the THD-1 to 0.0007%.
Cheers,
Bob
That is true. However, if the real amplifier shows the distortion effect Self described, and that amplifier as simulated does not, then we sill probably have not learned what the dominant source of the distortion increase is. If the real amplifier shows little or none of the effect Self described, then we can cross it off to a mistake on Self's part or an inappropriate generalization he made about the phenomenon. For example, there could have been something in the test setup or in the way that the distortion was being measured. A bit of capacitive coupling in a very small amount from a nonlinear output stage voltage would produce the effect, for example.
The output stage and its strays are usually the biggest source of distortion in an otherwise well-designed amplifier. A good distortion sanity check on an amplifier is to run it and close the loop without the output stage connected or operating. Run the drivers in class A with two equal emitter resistors in series between the driver emitters. Use the signal at the thus-created center tap to feed the feedback loop. This will tell you how well the overall amplifier up to the output stage performs.
Also, always bear in mind that the VAS output voltage is moderately distorted. Indeed, the THD seen on the VAS signal will usually be about equal to the open-loop THD of the output stage if the amplifier's negative feedback has reduced the amplifier's distortion to a small level. The VAS THD will be approximately the inverse of the open-loop distortion of the output stage. If any of this distorted VAS signal makes its way back to the input stage outside of the feedback loop, it may introduce distortion. Similarly, some of the currents running around in the VAS can be distorted due to the nonlinear loading of the VAS by the output stage. This will especially be the case for an amplifier that has only a double EF output stage.
Cheers,
Bob
