My main Leach amplifier was built with a massive power supply, dual mono chassis. I had 8 (that's eight) 30,000 uF capacitors to play with so I used 'em all, and tied all them with a single 3/16" aluminum ground plate. Looked neater that way and I was hoping for a minimum impedance ground, with the transformer center taps on one side and the star audio ground on the other side of the plane away from the current pulses. Turn-on charging current is (somewhat) limited by a double throw center-off switch that momentarily inserts a power resistor in the AC line--that first halfwave is a killer.
Later on, I read about the star-on-star ground (Cordell and elsewhere) and used .27 ohm power resistors to make a sort of pi filter to further isolate the input from the snubbered soft recovery rectifiers. Each capacitor has a 1 uF polypropylene bypass on its terminals. The resistor does very visibly reduce 120 Hz ripple, and I hope this layout has good high frequency performance as well.
I had thought of replacing the aluminum plate with copper--even silver plated copper, but I doubt it's really worth the trouble. (Somewhere, someone's done this in solid silver; I can't afford such madness, however tempting it may be.) Cutting slots in the ground plane to further isolate current pulses might be a small improvement, but I haven't thought my way through this tweak, I just left it a solid piece.
Does this sound like an effective strategy, if a bit overkill? It's huge, and modern electrolytics are dramatically smaller these days. I'm sure 10,000 uF or so per capacitor is probably sufficient. At any rate, the amplifier seems to have a very quiet background, no doubt helped by further RC filtering on the driver boards.
The main point of this exercise was to keep the noisy charging currents isolated from the audio ground and I hope that's what I accomplished, but impedance is a much trickier thing than simple DC current and ohmic resistance.
Later on, I read about the star-on-star ground (Cordell and elsewhere) and used .27 ohm power resistors to make a sort of pi filter to further isolate the input from the snubbered soft recovery rectifiers. Each capacitor has a 1 uF polypropylene bypass on its terminals. The resistor does very visibly reduce 120 Hz ripple, and I hope this layout has good high frequency performance as well.
I had thought of replacing the aluminum plate with copper--even silver plated copper, but I doubt it's really worth the trouble. (Somewhere, someone's done this in solid silver; I can't afford such madness, however tempting it may be.) Cutting slots in the ground plane to further isolate current pulses might be a small improvement, but I haven't thought my way through this tweak, I just left it a solid piece.
Does this sound like an effective strategy, if a bit overkill? It's huge, and modern electrolytics are dramatically smaller these days. I'm sure 10,000 uF or so per capacitor is probably sufficient. At any rate, the amplifier seems to have a very quiet background, no doubt helped by further RC filtering on the driver boards.
The main point of this exercise was to keep the noisy charging currents isolated from the audio ground and I hope that's what I accomplished, but impedance is a much trickier thing than simple DC current and ohmic resistance.
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Cutting slots in a ground plane will create eddy currents around the slote and thus inductance. Therefore, not a good idea for a low Z ground plane.
However, if one finds yourself with only able to use one ground plane, slots or trace cuts in strategic places can help direct currents and avoid crosstalk.
On the caps.... 10K is minimum, while more than 100K mfd is the point of little improvment for a lot more money. [Based on my tests].
THx-RNMarsh
However, if one finds yourself with only able to use one ground plane, slots or trace cuts in strategic places can help direct currents and avoid crosstalk.
On the caps.... 10K is minimum, while more than 100K mfd is the point of little improvment for a lot more money. [Based on my tests].
THx-RNMarsh
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What I read was that holes in a ground plane would not affect performance as long as they were not larger than 1/20 the wavelength of the signal in question. I can't think of why a perforated plane would not have more inductance than an ordinary plane though. It would certainly have more resistance.
That's not massive.
That normal for a stereo 3+3 ohms speaker rating.
3ohms and 60mF on each supply rail gives an equivalent PSU RC of 180ms. That perfectly suits an input filter RC of <90ms.
I use 8ohms speakers and generally use 20mF to 25mF on each supply rail for RC values of 160ms to 200ms. Two channels of +-20mF adds up to 80mF in the amplifier. If I were using 4ohms speakers I would double the capacitance (160mF) to retain the same RC time constants.
It's an actual experimental demonstration, and shows the same behavior.
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How do the mere humans 'see' the current flow in this demo?
- Is it some special paint that changes colour when it is on top of metal with current flowing?
- Or is there a special very small probe that can be used to show the current vector in underlying metal?
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In the meantime, here is a presentation showing a similar visualization, and data on a machine that does this.
https://www.youtube.com/watch?v=rSgl5Bt2OUw
Product information?Integral Geometry Instruments, LLC
LTP tail current
Hi Bob
The examples in your book (I'm referring to the schematics in Chapter 3 specifically) all feature very high LTP degeneration (470R emitter resistors) and a 1mA tail current, which is relatively low for a degenerated LTP.
Self on the other hand runs the LTP much hotter at approx 4mA and I suspect would run them even hotter if the packages permitted. He suggests 68-100 Re as a practical compromise between LTP linearity and voltage noise in the degen resisters at those currents.
Bonsai from these forums takes it to the extreme and runs the LTP super hot @ ~10mA
In my circuits I try to keep TO-92 Pd to < 100mW or thereabouts, since any higher and the device feels too hot to the touch. That correlates approximately with Self's examples.
Intuitively, I would think the tail current should be as high as practical (appropriately degenerated) to maximise drive into Cdom.
Can you shed any light on your philosophy?
Cheers
Christian
Hi Bob
The examples in your book (I'm referring to the schematics in Chapter 3 specifically) all feature very high LTP degeneration (470R emitter resistors) and a 1mA tail current, which is relatively low for a degenerated LTP.
Self on the other hand runs the LTP much hotter at approx 4mA and I suspect would run them even hotter if the packages permitted. He suggests 68-100 Re as a practical compromise between LTP linearity and voltage noise in the degen resisters at those currents.
Bonsai from these forums takes it to the extreme and runs the LTP super hot @ ~10mA
In my circuits I try to keep TO-92 Pd to < 100mW or thereabouts, since any higher and the device feels too hot to the touch. That correlates approximately with Self's examples.
Intuitively, I would think the tail current should be as high as practical (appropriately degenerated) to maximise drive into Cdom.
Can you shed any light on your philosophy?
Cheers
Christian
Lifetime for small-signal transistors below 125C is generally not a concern as I understand, so if the transistor behaves well at high temperatures and you can manage the heat and make sure the transistor cannot experience excess temperatures and will not cause problems with surrounding materials exposed to heat, then you can probably run it as hot as you want.
Of course with hot transistors, thermal drift can be quite a lot.
Of course with hot transistors, thermal drift can be quite a lot.
I indeed run the LTP 'rich' at 10 mA - so 5 mA per side. This allows me to acheive very high SR's (I use fully balanced designs exclusively) with conventional MC. Power dissipation in the LTP transistors is not a problem because you can always cascode them if your supply rails are high - this is exactly what I did on my e-amp and on the Ovation 250. With a 12 Volt cascode and 5 mA the device standing dissipation is 60 mW - close thermal proximity and good layout will largely cancel 1st order drift effects so thermally its quite stable (but not as good as a diamond buffer in my experience)
Of course, if you run the LTP rich, then with the BIP I/P you need to think about the bias currents as well. For the LTP devices I use BC547C and 557C or their SMD equivalents) so the bias currents are reasonably low, and you do get partial base current cancellation by using the fully balanced topology.
I think the most important thing for the LTP is that is remains in its linear operating region in the presence of a fast rise time signal. You can acheive this through a combo of degeneration, LTP current value and input BW filtering.
As to the exact value of the LTP current, that is usually a choice the designer makes considering all the other factors at play - there are no hard and fast rules.
Of course, if you run the LTP rich, then with the BIP I/P you need to think about the bias currents as well. For the LTP devices I use BC547C and 557C or their SMD equivalents) so the bias currents are reasonably low, and you do get partial base current cancellation by using the fully balanced topology.
I think the most important thing for the LTP is that is remains in its linear operating region in the presence of a fast rise time signal. You can acheive this through a combo of degeneration, LTP current value and input BW filtering.
As to the exact value of the LTP current, that is usually a choice the designer makes considering all the other factors at play - there are no hard and fast rules.
Thanks Bonsai.
I like to keep things simple and avoid using cascodes in the diff amp, so the LTP transistors would need to pass in the order of 350mW, even in a low power 50W circuit, according to your design criterion. 350mW from a 500mW Pd rated device seems like an awful lot when even 200mW is uncomfortably hot to touch in my experience.
It is not difficult to achieve >60V/us from a simple single-ended design, with simple MC, and conservative gain crossover ~500kHz. So long as there is a comfortable SR margin so the amp isn't into SR limiting, I'm not sure what there is to gain by pushing up the SR further? I normally set the input filter to about 1 - 2 decades outside the audible band so 0.2-2 Hz and 0.2-2Mhz. Does this all sound reasonable or have I missed the mark?
I like to keep things simple and avoid using cascodes in the diff amp, so the LTP transistors would need to pass in the order of 350mW, even in a low power 50W circuit, according to your design criterion. 350mW from a 500mW Pd rated device seems like an awful lot when even 200mW is uncomfortably hot to touch in my experience.
It is not difficult to achieve >60V/us from a simple single-ended design, with simple MC, and conservative gain crossover ~500kHz. So long as there is a comfortable SR margin so the amp isn't into SR limiting, I'm not sure what there is to gain by pushing up the SR further? I normally set the input filter to about 1 - 2 decades outside the audible band so 0.2-2 Hz and 0.2-2Mhz. Does this all sound reasonable or have I missed the mark?
50W into 8ohms with a BJT EF output stage would need quiescent supply rails about +-35Vdc, sagging to ~+-32Vdc when under full power testing.
35Vcc for a 5mA input transistor amounts to 175mW, =10mA tail current.
That is OK for a 500mW to 600mW To92 device.
The VAS device is the problem, 10mA @ 35Vce and requires parameters similar to a good To92, is where the Zetex Eline, or To126 earn their keep.
I use 1.5 - 2Hz to 160k - 250kHz as passive input filtering in a Power Amplifier. But the amplifier must perform well beyond these limits.
35Vcc for a 5mA input transistor amounts to 175mW, =10mA tail current.
That is OK for a 500mW to 600mW To92 device.
The VAS device is the problem, 10mA @ 35Vce and requires parameters similar to a good To92, is where the Zetex Eline, or To126 earn their keep.
I use 1.5 - 2Hz to 160k - 250kHz as passive input filtering in a Power Amplifier. But the amplifier must perform well beyond these limits.
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Thanks Andrew, quite right, my math isn't up to scratch: I forgot to divide by 2. Nevertheless, a little hot for my liking.
What is wrong with the KSA1381/KSC3503 crt driver? Low Cob, generous Vce, good fT, hFe and Early voltage. Seems to be the DIY audio favorite VAS. I use this with a 992/1845 follower and it sounds lovely.
What is wrong with the KSA1381/KSC3503 crt driver? Low Cob, generous Vce, good fT, hFe and Early voltage. Seems to be the DIY audio favorite VAS. I use this with a 992/1845 follower and it sounds lovely.
1381/3503 is good and has a no sink rating of 1200mW. The PNP Cob is >5pF @ 10Vce, too high compared to the few that are <3pF.
But some/many parameters will be compromised by achieving the 300Vce0 rating.
If this was re-designed for <200Vce0, could it be even better?
I generally aim for SR's of 1-2V/ us per peak output voltage - since the designs I've referenced are both quite high power the one has 80 V/us and the other 150 V/ us. There's nothing wrong with a bit more or a bit less either of course - it's a design choice.
Personally, I would not run the LTP at high voltages and high currents - even within dissipation limits since there will be warm up offset drift to deal with unless of course you run the LTP lean - but SR then has to be factored in. Another reason for the cascode of course is that you can get substantially better PSRR. See Dymond and Mellor for a full expose.
500 kHz ULGF seems low in the context of modern output devices.
Re amplifier BW limiting filter, I normally set it between 150 kHz (eg Ovation 250) and 1.5 MHz (sx-Amp) so quite similar to your guidelines.
Personally, I would not run the LTP at high voltages and high currents - even within dissipation limits since there will be warm up offset drift to deal with unless of course you run the LTP lean - but SR then has to be factored in. Another reason for the cascode of course is that you can get substantially better PSRR. See Dymond and Mellor for a full expose.
500 kHz ULGF seems low in the context of modern output devices.
Re amplifier BW limiting filter, I normally set it between 150 kHz (eg Ovation 250) and 1.5 MHz (sx-Amp) so quite similar to your guidelines.
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I found the paper in question through Edmond Stuart's website, and I must say it is the best 12 pages I've read in a while. Thanks for the heads up Bonsai!
I prefer economical designs and have been a little down on cascodes in general. I couldn't justify the added complexity, just to be able to use low noise transistors with low breakdown voltages. Well figures 16 and 18 plainly show how dramatically they, along with the improved Cdom connection, improve negative rail PSSR - about 40dB at 10kHz!
The schematic at figure 17 is similar to one in Cordell's book, and I have some reservations about enclosing three transistors in the miller loop. Is this stable in practice and are there any special precautions that need to be taken?
In my Lin/Blameless derivatives (conventional orientation with PNP input transistors) I don't bother RC decoupling the +ve rail connection from the output stage to the front-end, relying instead on the input and VAS current sources to clean up the supply. But the -ve rail to the input/VAS is heavily decoupled with a 10R & 1m to give a long time constant with minimal headroom loss. I believe this RC decoupling makes an audible difference.
This simple RC filter probably doesn't yield anywhere near the PSSR gain vs. the cascode arrangement, but it is very simple with only two devices and can be tuned for minimal Vdrop, while the cascodes probably give up more headroom, which is significant in my mind, particularly in a low power design.
A third benefit of the cascoded LTP is the opportunity to run high tail currents without excessive LTP dissipation. In my designs I run the tail current 4-6mA for per-transistor Pd between 100-150mW. I never bother to match the devices and have never had a problem with thermal drift. The only precautions I have taken is to pick the parts from the same tape, glue them back-to-back, and position them on the board as best I can away from other heat sources, and behind other (larger) components to minimise UV effects. Output offset is reliably <10mA with the On Semi and Fairchild devices I have used and never drifts more than a few mA.
It also occurred to me while thinking about your "supercharged" input pair, that the CCS pass transistor would need to be uprated to handle the extra Pd at 10mA. I see in your schematic that you've used a TO-126 but it occurred to me that you could instead use two TO-92 in cascode. I already use voltage divider resistors around the cap to stabilise the base currents, a la Self's circuits, so the CCS cascode could be added with no additional passives, and has the secondary benefit of a greatly increased output impedance vs. a single TO-126. That way the two CCS pass transistors and two LTP cascodes would all have approx. equal Pd.
Yes, I agree that 500 kHz conservative, but I have found in practice to be not far off the mark (and a safe starting point) if you are working with slow outputs. For example, I'm rather partial to the MJL21193/4 pair, which has an fT of only 4MHz but are tough as old boots and perform beautifully in a simple EF2 design if you work within their limits.
But I have found them to be absolutely hopeless in an EF3 configuration: the only way to stabilise the thing was to drop the ULGF to ~250kHz or slug the drivers with a heavy Cbc. I believe there has been angst amongst some of the builders in the EF3 Slewmaster thread and some of their findings correlate with my own.
But I think the newer 30MHz ring emitter transistors are a better prospect for new designs, and I have successfully used these in very simple EF type 2 projects with careful attention to layout and a gain crossover approaching 3 MHz. This is with the NJW1302/3281, KSA1220A/2690A 175 MHz drivers, and suitably fast silicon in the rest of the signal path. It seems effortless to get a good performance from a simple circuit under these conditions.
One thing that bothers me in my experiments with the EF3 is that I seem to have to sacrifice the ULGF by as much as 50% vs. the EF2 equivalent but this does not seem to enter into the discussion when people compare these two topologies. I'm not sure why local stability of the local EF is effected by the gain crossover point; however, the influence is real and also seems to effect compound pair output stages, albeit to a much lesser degree.
I prefer economical designs and have been a little down on cascodes in general. I couldn't justify the added complexity, just to be able to use low noise transistors with low breakdown voltages. Well figures 16 and 18 plainly show how dramatically they, along with the improved Cdom connection, improve negative rail PSSR - about 40dB at 10kHz!
The schematic at figure 17 is similar to one in Cordell's book, and I have some reservations about enclosing three transistors in the miller loop. Is this stable in practice and are there any special precautions that need to be taken?
In my Lin/Blameless derivatives (conventional orientation with PNP input transistors) I don't bother RC decoupling the +ve rail connection from the output stage to the front-end, relying instead on the input and VAS current sources to clean up the supply. But the -ve rail to the input/VAS is heavily decoupled with a 10R & 1m to give a long time constant with minimal headroom loss. I believe this RC decoupling makes an audible difference.
This simple RC filter probably doesn't yield anywhere near the PSSR gain vs. the cascode arrangement, but it is very simple with only two devices and can be tuned for minimal Vdrop, while the cascodes probably give up more headroom, which is significant in my mind, particularly in a low power design.
A third benefit of the cascoded LTP is the opportunity to run high tail currents without excessive LTP dissipation. In my designs I run the tail current 4-6mA for per-transistor Pd between 100-150mW. I never bother to match the devices and have never had a problem with thermal drift. The only precautions I have taken is to pick the parts from the same tape, glue them back-to-back, and position them on the board as best I can away from other heat sources, and behind other (larger) components to minimise UV effects. Output offset is reliably <10mA with the On Semi and Fairchild devices I have used and never drifts more than a few mA.
It also occurred to me while thinking about your "supercharged" input pair, that the CCS pass transistor would need to be uprated to handle the extra Pd at 10mA. I see in your schematic that you've used a TO-126 but it occurred to me that you could instead use two TO-92 in cascode. I already use voltage divider resistors around the cap to stabilise the base currents, a la Self's circuits, so the CCS cascode could be added with no additional passives, and has the secondary benefit of a greatly increased output impedance vs. a single TO-126. That way the two CCS pass transistors and two LTP cascodes would all have approx. equal Pd.
Yes, I agree that 500 kHz conservative, but I have found in practice to be not far off the mark (and a safe starting point) if you are working with slow outputs. For example, I'm rather partial to the MJL21193/4 pair, which has an fT of only 4MHz but are tough as old boots and perform beautifully in a simple EF2 design if you work within their limits.
But I have found them to be absolutely hopeless in an EF3 configuration: the only way to stabilise the thing was to drop the ULGF to ~250kHz or slug the drivers with a heavy Cbc. I believe there has been angst amongst some of the builders in the EF3 Slewmaster thread and some of their findings correlate with my own.
But I think the newer 30MHz ring emitter transistors are a better prospect for new designs, and I have successfully used these in very simple EF type 2 projects with careful attention to layout and a gain crossover approaching 3 MHz. This is with the NJW1302/3281, KSA1220A/2690A 175 MHz drivers, and suitably fast silicon in the rest of the signal path. It seems effortless to get a good performance from a simple circuit under these conditions.
One thing that bothers me in my experiments with the EF3 is that I seem to have to sacrifice the ULGF by as much as 50% vs. the EF2 equivalent but this does not seem to enter into the discussion when people compare these two topologies. I'm not sure why local stability of the local EF is effected by the gain crossover point; however, the influence is real and also seems to effect compound pair output stages, albeit to a much lesser degree.