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Old 28th April 2011, 07:58 AM   #1661
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A second stage with both emitter follower and cascode is prone to local instability, which is indicated by the 50 MHz peak you see. Some randomly placed RC networks may, at least in simulation, mitigate the effect. But a far more powerful technique, used extensively in IC opamps but apparently mostly unknown to audio designers, is the use of a feed-forward capacitor at the emitter follower. For the schematic you posted in the other thread this would mean a capacitor (roughly 100 pF) from the base of Q19 (Q20) to the base of Q21 (Q22).

Also the capacitors from the current mirror inputs (C5 and C6) to ground look dubious to my eyes. Any reason for these? Also I'm not sure if it is a smart idea to implemented the amp without output stage; the second stage output node might be rather sensitive to capacitive loading. Use a small-signal class A emitter follower for prototyping.

Samuel
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Old 28th April 2011, 12:22 PM   #1662
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Hi there,

First of all, I am happy to see Edmond is back on the forum since most of my actual schematic has been discussed with him.

As for the utility of the RC network in simulation it seems indeed rather of lower effect. Or effect in a less important portion of the graphs. However I built once one of those circuits. And also getting back to Samuels comment it indeed helps to lower / annulate oscillations which are like bursts on the scope. I can only guess it is indeed a local oscillation. What I can say for sure is that they have quite effect in reality.

As for the caps to ground in the IPS their effect is indeed very small in simulation and also in my previous pcb, they didn't have any noticeable effect. But I guess they are only useful in case of instability resulting from complex parameters and that in my case they were not needed.

I have a small OPS which is not implemented in this schematic nor in the pcb. I can connect it to the test pcb. I need however a jumper set in the pcb to make it easy. Or I can include the whole stuff on the pcb itself. Mmm I had troubles getting everything fitted on a 100x140mm pcb ... maybe I need to remove fuses and lower rail cap sizes ... it is a prototype anyway and will always be used with a bench powersupply (limited current).

I will check out what your solution brings in the simulation : 100pF between bases of Q19 & Q21 respectively Q20 & Q22



Cheers,

Olivier
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Old 28th April 2011, 12:40 PM   #1663
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Quote:
Originally Posted by Samuel Groner View Post
A second stage with both emitter follower and cascode is prone to local instability, which is indicated by the 50 MHz peak you see. Some randomly placed RC networks may, at least in simulation, mitigate the effect. But a far more powerful technique, used extensively in IC opamps but apparently mostly unknown to audio designers, is the use of a feed-forward capacitor at the emitter follower. For the schematic you posted in the other thread this would mean a capacitor (roughly 100 pF) from the base of Q19 (Q20) to the base of Q21 (Q22).
Hi Samuel,

Indeed, those feed-forward capacitors are quite effective in suppressing local instability. More recently, by placing caps more or less 'randomly', I discovered this too.

On the other hand, according to Glen Kleinschmidt, a RC network at the input of the VAS serves one more purpose: reducing the susceptibility to HF ingress.

Quote:
Also the capacitors from the current mirror inputs (C5 and C6) to ground look dubious to my eyes. Any reason for these?
Those caps vastly improve the PSRR at AF/HF. Remember, Cdom is referenced to the supply rails (instead of gnd), hence....

Quote:
Also I'm not sure if it is a smart idea to implemented the amp without output stage; the second stage output node might be rather sensitive to capacitive loading. Use a small-signal class A emitter follower for prototyping.

Samuel
That's what I told him too.

Cheers,
E.
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Old 28th April 2011, 01:27 PM   #1664
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Those caps vastly improve the PSRR at AF/HF.
I'm aware of this, but then they also affect open-loop gain. It's been years back since I've looked into this, but IIRC the effect was gross enough to make the technique unusable.

Samuel
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Old 28th April 2011, 06:08 PM   #1665
masood is offline masood  India
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can anybody will send dr. batra's amplifier circuit/pcb especially.
awaiting curiously masood email khan.shahid251@gmail.com
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Old 28th April 2011, 06:13 PM   #1666
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Default unusable?

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Originally Posted by Samuel Groner View Post
I'm aware of this, but then they also affect open-loop gain. It's been years back since I've looked into this, but IIRC the effect was gross enough to make the technique unusable.

Samuel
At frequencies of interest the effect is virtual zero (at least in this application). Even at 10MHz the OLG is only 0.4dB less. Is that what you call gross enough to make the technique unusable?

Cheers,
E.
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Old 28th April 2011, 06:38 PM   #1667
jcx is online now jcx  United States
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a quick estimate is that it rolls of 1/2 of the diff pair current starting at the pole of the C with the mirror input resistance

good practice will have some V gain between the diff pair degen and and the mirror degen to keep mirror noise contribution low

so the pole may be ~2-4x below unity gain - but power amps typically are ran at Av ~20 or more so the added pole will typically be 4x or more higher than the loop gain intercept frequency (all assuming dominant pole Miller comp)

the added phase shift at the intercept frequency would be <10 degrees - so the added psrr compensation C at the mirror input shouldn't cut available bandwidth by much either


it could be an unacceptable cost at lower/unity closed loop gain

Last edited by jcx; 28th April 2011 at 06:43 PM.
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Old 28th April 2011, 07:03 PM   #1668
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It might be that I looked at this for an amp with either low closed loop gain, or unusually high current mirror impedance. Don't recall.

Samuel
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Old 28th April 2011, 07:25 PM   #1669
masood is offline masood  India
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what will be called when npn tr. are in both channel this type of amplifier
plz explain
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Old 28th April 2011, 09:16 PM   #1670
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Hi Samuel,
I replaced the RC network with the 100pF capacitor between bases of the darlington vas transistors. The result is very similar. It eliminates the gain peak @ 50MHz just like the RC network did before.
I am mitigated about implementing both options on the pcb because I am willing to reduce optional tracks as I fear they make opportunities for problems.
Greetz,
Olivier
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