No, it is by far the best circuit you've posted in this thread.
What do this figures tell you if we consider that a single 2SK170 has about 1 nV/sqrt(Hz)? That there are other noise sources which dominate things even with 3 JFETs. The main problem with your plan is that R3 is way to low to make the noise contribution of U1/U2 negligible; however you can't make it much larger because the JFETs are running at Idss.
The following changes should lead to a better plan:
* The gates of the JFETs should be bias slightly negative (say -300 mV) to reduce their drain current to about 1.5 mA each. That's easily done with a voltage divider from the negative supply connected to R2.
* R3 should then be selected to operate the JFETs at about 5 V drain voltage. I suggest you use 4 JFETs only which gives about 1k Ohm for R3.
There's more to say about second-order noise contributions but let's first fix that one.
That's why I said keep PSRR high. The very low noise figures some papers quote are only valid if the battery is fresh and no significant current is drawn; both assumptions are not valid here. To make PSRR somewhat better increase R3 (as covered above) and remove R12.
Samuel
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I've quickly simulated the PSRR of your latest design. There is actually substantial gain (roughly 40 dB) from the positive rail to the output which places unreasonable constraints on the noise of the power supply. You really need to improve PSRR, mainly by increasing R3.
Samuel
Samuel
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Dave Davenport's "Grounding and Shielding" article on DIYAUDIO -- is must reading: http://www.diyaudio.com/forums/diya...-grounding-interconnection.html#content_start
That is pretty much my HPS 5.0 input stage, minus the power buffer required to drive the low feedback resistor(not required here) http://www.diyaudio.com/forums/analogue-source/166037-hps-5-0-a.html#post2171028
Has virtually zero PSRR, which explains the sensitivity to power supply noise (so much for quiet lead-acid cells). The "unreasonable constraints on the noise of the power supply" are addressed in HPS 5.0 by a noise cancelling power buffer (essentially greatly reducing the power device Rbb by including it in a local current feedback loop). Any other solution (shunt, series, etc... regulator) will fail here. A simple power follower could be acceptable, depending on the power device used).
Increasing R3 will only marginally improve the PSRR, it will still remain positive (and act as a noise gain).
all the noise and distortion within the audio band at the output of U2 is injected back into U1.
It does not appear to me that the noise at the output is attenuated by 160dB before being injected into U1.
The input signal to U2 is attenuated by 160dB (if your calculation is correct) by the time it appears at the output. That is quite different.
Look at it again--the output of the servo amp is referred to ground at audio frequencies because he omitted the LP filter from your schematic. PSRR improves in proportion with R3. Ideally we want a CCS there but that takes some efforts to make low noise.
Increasing R3 surely reduces noise--this is a current node (covered before in this thread).
Samuel
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Summary
The good:
* measured 0.5nV/rtHz
* simple to build and get to work
The bad:
* lacking in PSRR
* batteries are annoying
Suggestion from Salas and Joachim: RC or capacitor multiplier filter.
Suggestion from Samuel: increase PSRR via larger drain resistor and
lower jfet current.
Suggestion from syn08: use active filter.
OK, at this point lowering the noise would not be so much of a
priority, I think I can live with 0.5nV/rtHz. The most annoying thing
is USING BATTERIES. Charging, using them, then oops, they're
discharged and the noise is up. I think I see why syn08 hates
batteries. Basically I think the circuit would benefit most from a
quiet psu and better psrr. To be a lab preamp, it should be stable
and dependable and the last thing to worry about should be that the
batteries are charged or not.
syn08, I've tried a little earlier your filter, without the LM317 part
because I used a regulated lab power supply. The noise was still
quite a bit higher than using batteries only. You say a
filter/regulator like the one attached wouldn't work, but it has decent psrr.
Samuel, I'm going to try to change the circuit as per your suggestion with low jfet current, higher value R3, and some sort of divider at the jfet source for biasing.
The good:
* measured 0.5nV/rtHz
* simple to build and get to work
The bad:
* lacking in PSRR
* batteries are annoying
Suggestion from Salas and Joachim: RC or capacitor multiplier filter.
Suggestion from Samuel: increase PSRR via larger drain resistor and
lower jfet current.
Suggestion from syn08: use active filter.
OK, at this point lowering the noise would not be so much of a
priority, I think I can live with 0.5nV/rtHz. The most annoying thing
is USING BATTERIES. Charging, using them, then oops, they're
discharged and the noise is up. I think I see why syn08 hates
batteries. Basically I think the circuit would benefit most from a
quiet psu and better psrr. To be a lab preamp, it should be stable
and dependable and the last thing to worry about should be that the
batteries are charged or not.
syn08, I've tried a little earlier your filter, without the LM317 part
because I used a regulated lab power supply. The noise was still
quite a bit higher than using batteries only. You say a
filter/regulator like the one attached wouldn't work, but it has decent psrr.
Samuel, I'm going to try to change the circuit as per your suggestion with low jfet current, higher value R3, and some sort of divider at the jfet source for biasing.
Attachments
Absolutely, increasing R3 reduces noise. The noise is proportional to SQRT(R3) while the signal is proportional to R3, therefore the S/N increases (or the input referred noise decreases).
As I said, increasing R3 improves the PSRR (could be proportional, I don't know) but whatever R3 the PSRR will remain positive (that is, there is a gain > 1 associated with any PS perturbation, noise, etc...). Therefore, increasing R3 goes essentially nowhere. The upper value of R3 is limited anyway, by the requirement to bias the JFETs.
It is easy to improve PSRR by more than an order of magnitude by increasing R3. This reduces PSRR to less than -20 dB RTO. With an EIN of 0.5 nV/sqrt(Hz) this leads to << 50 nV/sqrt(Hz) PSU noise requirement. That's *much* more feasible than the initial << 5 nV/sqrt(Hz).
Samuel
Samuel, would you care to come up with some component values to support this claim? According to my calculation, for changing R3 from 100 to 200 ohm, the PSRR varies from +40dB to +20dB (so a net gain for the PS noise etc...). This is for a bias current of 80mA, can't go higher with R3 to keep some Vds and JFETs saturated.
If you mean like syn08's HPS 5.1, then the PSRR doesn't change almost at all.
Samuel, it appears that modifying the circuit to increase R3 significantly makes the jfet biasing a problem. The way you do it in your circuit is probably the right way, but I've had problems with your circuit too (it doesn't lend easily to a number of parallel jfets).
I'm assuming a total drain current of 6 mA. See some of my posts back where I show how to decrease Id to a sane value; there's little point in running them above 2 mA.
Ditto...
I don't see how paralleling transistors (and/or increasing the total drain current) should be a problem; what causes problems is lowering the feedback network impedance as one quickly needs very large capacitor values for good low-frequency response.
Samuel
Incorrect, Samuel.
The JFET has two noise sources: thermal noise and flicker (or 1/f^n) noise.
The thermal noise density follows the well known law Et=SQRT(4kT*Rch), where Rch is the channel resistance and computes to approximately (2/3)/gm. The larger the transconductance, the lower Rch and therefore the thermal noise.
The JFET flicker noise density is SQRT(4kT*Rch*(1+(fc/f)^n)) where fc is the corner frequency, that is, the frequency at which the thermal and flicker noise are equal.
As you see, both noise sources decrease as SQRT(1/gm). The whole point of paralleling JFETs is to create an equivalent large transconductance, therefore reduce Rch and the thermal noise.
Now, the JFET transconductance is approximately gm=2*Id/Vt where Vt is the pinch voltage. Therefore, the transconductance increases proportionally with Id or proportional to the number of paralleled JFETs. As a result, the equivalent input noise of the JFET common source gain stage decreases with SQRT(Id) or decreases with SQRT(N) where N is the number of paralleled devices.
Decreasing the drain current and increasing R3 actually increases the equivalent input noise.
Your analysis lacks e.g. the consideration of equivalent gate series resistance. The resulting flattening of the voltage noise vs. Id curve is e.g. seen in the 2SK170 datasheet on page 3.
Samuel
Samuel