BJT EF Output stage bias distribution?
I'm having trouble with On Semiconductor MJL1302A/MJL3281A used as output devices. I acquired a lot of these devices. They are advertised as direct replacements for the old and well-known Toshiba 2SA1302/2SC3281, of which only fakes are available today.
In my circuit, I have three in parallel on each rail. I'm aiming for 300mA of total bias for the output stage. However, with devices from the same date code, I get quite large variations in the current through individual devices. I see anything from 8mV to 14mV accros the 0,1R emitter resistors when I adjust for 300mA current drain of the output stage.
Is this normal for these kinds of devices?
Do you select output devices?
Does the difference become smaller with higher currents?
Before I start further testing, do you think it matters?
I have never experienced these problems with other devices before.
This is a very old topic on here.
Some people demand tightly controlled transistors and others dont think it matters much.
The emitter resistors are supposed to help balance things out a bit.
I did remake it later with new devices from the same "batch" , but it showed no undue stress while mismatched.
Current sharing stability depends on power supply voltage and non-shared thermal resistance too. It gets worse towards higher voltages and higher thermal resistances.
What kind of insulators, if any, are you using? How high is the power supply voltage? Having 0.1 ohm emitter resistors sounds quite low, but if power supply voltage isn't too high it could work.
100mA bias per pair with 0.1R is about half of what you should be running for "optimal bias", and is significantly underbiased.
Better to be slightly over biased than under. If the extra heat of a 600mA Iq can't be tollerated, I'd increase the emitter resistors to at least 0.22R.
In this case also this thread could be of interest:
the differences you re measuring are quite common in
devices dispersion...these are differences in vbe, and are even
lower than the dispersion we find in diodes jonctions of the same device..
as the others are telling you, your parallel devices have not been matched.
If you want optimal operation from parallel devices you must match them.
You can use your completed 3pair PCB as your test device. But I'd suggest that each group of DUTs are attached with short leads to save the PCB and the devices from damage when you try to remove them.
Set up your PCB Vbe to give the bias you need. Don't change it.
Attach your DUTs. Measure Vre. Remove and group the DUTs by Vre readings.
Select PNP DUTs that have very similar Vre readings and select NPN DUTs that have similar (but not necessarily the same as PNP) and attach your 3pair of these selected devices to your test PCB.
measure the Vre. You should find that the devices Vre is now very much closer together. If they are within 10% total spread you can stop. If you are <5% total spread you have an excellent match of Vbe.
If you are around 20% spread then a second set of DUT testing is looming in.
Now to an optimum ClassAB bias current.
The Vre of the external resistor and the effective internal resistor should be 26mV when the transistor is cold (Tc=25degC). This falls slightly as the Tc & Tj rises.
Assuming Re=0r22 and that the transistor has an effective re=0r04, then total Re+re=0.26ohms.
The required bias voltage across Re is 22/26 * 26mV ~=22mV
Set Vre to average 22mVre across the 3devices.
If you decide to use Re=0r1 then try setting Vre to ~18mVre. This will require a heatsink about twice as big.
I would recommend 0.22 ohm emitter resistors if you have not matched the transistors. 100mA bias per pair is fine.
I usually find 5mA through each MOSFET is enough to get rid of crossover distortion.
Any more is just wasted as heat.
I use a sig gen and a scope, apply a 1 volt sine wave and monitor the output into a speaker. I turn the bias up slowly until the sine wave is no longer distorted and leave it there.
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