Improving the linearity of an N-ch MOSFET output stage

[x-pro]

I am happy to invite forum members to have a look at my short article:

http://www.ant-audio.co.uk/Theory/N-channel D-MOSFET output stage with improved linearity.pdf

In this thread I will try to answer questions about that circuit configuration and also about the last diagram from the article - a practical example of an output stage that can be used with or without an overall NFB with either tube or solid-state VAS. I attach this circuit diagram here as well.

Alex Nikitin

 

[x-pro]

Simulation Results

I did a simulation in LT spice of two versions of my circuit configuration, using andy_c N-MOSFET model for 2SK1530 from this post:

http://www.diyaudio.com/forums/showthread.php?postid=1316183#post1316183

Here is the result. The idle current of the output transistors is set for 70mA, DC conditions on the output are set at less than 1mV offset. The rest is clear from the SPICE parameters. From the FFT graph the distortion reduction due to the additional FET on the left is up to 40 dB for odd order components.

Alex

 

[Francois G]

Performance figures

Thanks for sharing your circuit. It looks very interesting, especially due to my interest in tube voltage amplification. Do you have any test or simulation results for the final circuit?

I'm not an electrical engineer and I'm looking forward to learn more in this discussion group about you circuit and similar ones. That said, your design looks similar to the amplifier Wim De Haan published in audioXpress about 18 months ago and a higher power version recently in Elektor and I thought you might enjoy comparing them.

Both the NISHIKI and MUGEN designs are hybrid amplifiers without global feedback using quasi-complementary output stages. The website does not show the schematic because it was published in the Elektor October 2007 issue. The topology is shown on his website at http://www.wimdehaan.nl/ under the NISHIKI heading.

The website has extensive test results for these amplifiers using different tubes and other options.

 

[Francois G]

Results already!

You posted the sim results as I was writing my post (#3)! Thanks.

 

[Francois G]

After further investigation

I realized that the circuits are not so similar after reading your article. It seems that the means of achieving phase splitting is quite different, but I admit that I don't fully understand either circuit. So, I still looking forward to learning.

 

[x-pro]

Here is the result of another simulation run for the same two circuits - now for 20kHz.

Cheers

Alex

 

[sajti]

Hi,

this circuit looks nice! I will try to build it, with IRL540N, and IRF9520N.
My only question is: How can I use more output devices parallel? I need source resistors for that. But the voltage drop on this resistors can saturate the drivers, at the peak currents. Do You have any idea about it?

Sajti

 

[x-pro]

Hi,

this circuit looks nice! I will try to build it, with IRL540N, and IRF9520N.
My only question is: How can I use more output devices parallel? I need source resistors for that. But the voltage drop on this resistors can saturate the drivers, at the peak currents. Do You have any idea about it?

Sajti

Hi Sajti,

yes, you can build the circuit from the first post with IRL540N on the output, providing you would not increase P/S voltage, however IRF9520 could be a bit too big - better to use 9510 or 9610. You are quite right that it is difficult to parallel devices in this configuration. Every circuit has it's strong and weak points. To increase the power of this circuit I had to use a series connection of two devices (what is usually called "totem pole"). Modern MOSFETs can pass a lot of current (HUF76639 is 50A device) so the current is not much of a problem - as shown the circuit can deliver about 20A peak current into 1 Ohm load. And the amplifer sounds better when devices are not connected in parallel.

The maximum output current in this circuit is quite accurately and symmetrically limited by 2Vth*S - that limit has negative temperature coefficient (as both Vth and S drop with temperature) which helps the amp to survive overload conditions. The circuit as shown would handle a short on the output for a second or two - enough for AC fuses on the output of the transformer to blow.

Few more important notes:

1) output devices should be mounted on a heatsink with less than 1C/W using mika or AlO insulation with thermal grease and not far one from another (about 25-30 mm between mounting screws) . No silicon impegnated washers, please - the amp will blow.

2) thermal sensing transistor Q1 should be attached to the heatsink between output devices and thermally connected to it using thermal grease.

3) VR1 bias adjustement pot should be a multiturn cermet type and before switching the amp on first time it needs to be in the "top" (i.e. max resistance) position. Adjust bias slowly - it is a very sharp adjustement. It is useful to look at the bias behavior during warm-up. It may be necessary to change the value of R4 a bit (i.e. 200-220-240-270 Ohm) to correct the current source temperature coefficient for a particular type of the output devices. If the bias increases with temperature you'll need to decrease the value of R4 and vise versa. Every time you change R4 you'll need to reset the pot and re-adjust the bias. It is useful to have a slightly negative TC.

Cheers

Alex

 

[lumanauw]

Hi, Xpro,

Is it possible to use bipolar in position of M3-M4 and omit D5-D6? Bipolar has bigger Gm than mosfet, will this affect something?
Oops, sorry. After reading your article, M3 and M2's Vgs must be matched. Bipolar only have 0V6, while mosfets need about 3-4V.

 

[x-pro]

Is it possible to use bipolar in position of M3-M4 and omit D5-D6? Bipolar has bigger Gm than mosfet, will this affect something?

There are several problems using bipolars for the differential stage. First, you'll need additional biasing (at least) for M4 position otherwise there would be not enough votage swing to operate M2 FET. More important that the base currents of bipolars would introduce an additional temperature dependant component into the bias of the output devices and will make it less stable. Without source resistors the performance and sound much better but the biasing is critical. There are some other issues as well. And you can not omit D5-D6 either with FETs or bipolars - otherwise o/p stage would destroy itself easily in a fault condition.

Oops, sorry. After reading your article, M3 and M2's Vgs must be matched. Bipolar only have 0V6, while mosfets need about 3-4V.

Vgs for M4 should be at least twice of Vgs for M1, M2 in idle condition. For devices as shown HUF76639 has Vgs about 1.7V and ZVP3310 - about 3.5V. M3 Vgs is not that important however it is useful to get it the same as for M4 - providing for near 0 DC offset from the input to the output and good circuit symmetry.

Cheers

Alex

 

[x-pro]

I did few more simulations using the circuit I've posted in another thread:

http://www.diyaudio.com/forums/showthread.php?postid=1337626#post1337626

Here are the results (THD figures taken from .four command output in LTspice)

Cheers

Alex

P.S. - that circuit is only for simulation - P-ch devices used there are rated at 60 V only. Spice does not care , but in practice different devices should be used.

 

[Fanuc]

Hello Alex,

Been having a careful look at your circuit, in particular the first one. The all N channel design with N chl phase splitter.

A couple of questions for you.

Do you think that the Zout on the drain/source nodes are different in a single fet phase splitter?. Remember someone mentioning this with the original JLH class A BJT design. Which then begs the question of using R/RC or step networks like in a Naim NAP250 to equalise the bandwidth. I think this bandwidth disparity would probably be exacerbated by not using global NFB -in push pull at least.

In fact I wonder if a LTP is even better in this respect, if at all.

Out of interest what sort of THD did you get for Fig 1. in the PDF file you link to ?

Also any ideas of effeciency. Mosfets do not have the beta droop of BJT's and a Hi Z output doesn't matter to me in my application. I fancy building it soon without global NFB. I have worried about this before in some designs, getting the right mix of drive current, bandwidth, slew rate etc and the outputs are in different modes of operation etc.

Just some thoughts

Kevin

 

[x-pro]

Hello Alex,

Been having a careful look at your circuit, in particular the first one. The all N channel design with N chl phase splitter.

A couple of questions for you.

Do you think that the Zout on the drain/source nodes are different in a single fet phase splitter?. Remember someone mentioning this with the original JLH class A BJT design. Which then begs the question of using R/RC or step networks like in a Naim NAP250 to equalise the bandwidth. I think this bandwidth disparity would probably be exacerbated by not using global NFB -in push pull at least.

In fact I wonder if a LTP is even better in this respect, if at all.

Out of interest what sort of THD did you get for Fig 1. in the PDF file you link to ?

Also any ideas of effeciency. Mosfets do not have the beta droop of BJT's and a Hi Z output doesn't matter to me in my application. I fancy building it soon without global NFB. I have worried about this before in some designs, getting the right mix of drive current, bandwidth, slew rate etc and the outputs are in different modes of operation etc.

Just some thoughts

Kevin

Hi Kevin,

that first circuit could be quite unlinear without a feedback and at low bias currents. However the transfer characteristic is reasonably symmetric between upper and lower halfs. If you increase the bias, the linearity is much better. I attach the simulation circuit and FFT result for 900mA bias 50 V p-p into 8 Ohm - Gain is about 50, THD is under 0.3%. Bandwidth at -3 dB is 300 kHz. The difference of Zout on the phase splitter is not a serious problem, as far as I can see.

Cheers

Alex

 

[Nelson Pass]

Why the diodes on the Sources of the input pair?

 

[x-pro]

Why the diodes on the Sources of the input pair?

Good question, Nelson!

First of all these are for protection. With diodes in place, the output current is limited symmetrically (though it could be up to 28-30 A peak with HUF76639 devices) and there is no chance to overvoltage the gates of the output devices. As a pleasant side-effect these diodes also improve the slew rate and keep it the same in both directions.

Cheers

Alex

 

[EUVL]

> With diodes in place, the output current is limited symmetrically (though it could be up to 28-30 A peak with HUF76639 devices) and there is no chance to overvoltage the gates of the output devices. As a pleasant side-effect these diodes also improve the slew rate and keep it the same in both directions.

I presume we are talking about D5 & D6 in Fig.6 of your PRF file ?
Then I do not understand why it protects gate overvoltage, and how it improves slew rate.

Would you be kind enough to elaborate ?


Patrick

 

[x-pro]

I presume we are talking about D5 & D6 in Fig.6 of your PRF file ?
Then I do not understand why it protects gate overvoltage, and how it improves slew rate.

Hi Patrick,

yes, Nelson asked about D5 & D6 of the circuit in the first post (and Fig 6 in PDF). I'll try to elaborate: under normal linear conditions the current from the current source on Q1, Q2 is split by the phase splitter between R6 and R8, creating the gate-source voltages for output MOSFETs. The sum of these two voltages in this case is always the same, if some voltage is added for Vgs of one device exactly the same amount is subtracted from another, providing for near-perfect push-pull operation.

However in case of an overload this balance would break because there are other ways for the current to flow - namely from the VAS through D3 (needed to protect the gate of M3) directly into R6 (this could be taken care of by limiting the VAS output current, but that would produce other negative effects, i.e. reduce the speed of the amplifier). Even more dangerous is a direct pass from the output through R6 and M3 into the gate of M1 when the circuit clips negative. Here the voltage on the gate could be near half supply in case of the short on the output and the current of M1 would be enormous, limited only by R11 (as the resistance of the M1 could be less than 0.025 Ohm). D5 protects from the first occasion during positive clipping and D6 - from the second, during negative clipping. With these 2 diodes in place, the gate-source voltage on either of the output MOSFETs can only be double of the idle value - thus limiting the current and protecting the gate at the same time.

The circuit as shown on that diagram, if made properly, can take a short circuit on the output for long enough for a slow-blow fuses to react on a secondary of the power transformer. Two diodes also work differentially in a normal operation reducing the influence of their unlinearity.

Now about the slew rate - again, without these diodes the circuit slews asymmetrically and can produce spikes of through-current. With D5, D6 in place the operation of two halfs is very symmetrical even in slewing. The positive slew rate is improved because during the positive-going transition D5 cuts out the capacitance of M3.

The speed of this circuit is about 35 V/us into 8-Ohm load, however as it depends only on the amount of current available form the current source and input capacitance of the output devices, it could be easily made into hundreds of V/us just by increasing that current. For a 50W amplifier that speed appears to be sufficient and we can use very simple CCS and driver stages without dissipating much heat.

Cheers

Alex

 

[KSTR]

Thank you very much for sharing these circuits, and the excellent explanation. I was wondering about those diodes, too. While I saw the possibility of the M4 body diode path, I didn't see the path from the driving stage nor the capacitance issue...

In between, I thought about adding a folded cascode (drawn open loop). Although it would add one stage inside the local FB loop, it might be of advantage (balancing the conditions for the LTP in some -- not all -- aspects), do you think this would be of any benefit?

- Klaus

 

[x-pro]

In between, I thought about adding a folded cascode (drawn open loop). Although it would add one stage inside the local FB loop, it might be of advantage (balancing the conditions for the LTP in some -- not all -- aspects), do you think this would be of any benefit?

Hi Klaus,

if you read my article (PDF link in the first post), you'll see a similar arrangement with a differential drive in Fig. 3 . There are quite a few practical implementations of this approach. You can drive the output as shown there in Fig 3, or you can drive it differentially, or you can use bipolar devices, folded cascode etc. The main difference in my circuit is a very short and effective local feedback implemented by connecting one side of a differential driver directly to the output, making an output stage into a very linear and practical power follower.

Cheers

Alex

 

[john-china]

i like your design very much,and ...

how much is the gain. and how to caculate it?