Boards for the latest HPS 3.3 phono stage are on order (6"x8" so I decided to use an overseas house to keep down the costs), so meantime here's what's on the board...
But before that, here's an HPS update: National Semiconductor is now manufacturing LME49610, a high current (250mA) buffer, also supporting +/-22V. This, in combination with the relatively new LME49860 dual opamp, also supporting +/-22V, allows simplifying the power supply, without any sacrifice in headroom. Noise performance is of course the same... Details to follow soon!
I was looking for some time to further develop an as much as possible simpler power amp, preferable with a higher power spec (compared to PGP and YAP), without compromising to much the performance. The new schematic is attached. I'm currently feeding this new design with +/-60V (that's how much I can get from my 2 x 600W lab supplies), plan is to go up to +/-70V. Here are some key measured specs of the new VSOP (Very Simple Output Powerstage) amp. Pretty good for 12 small signal trannies, plus the output devices, and an opamp. No overcurrent protection, not sure if all that extra circuitry required to make the amp fool proof is really required, anyway the YAP "hifi thyristor" circuit works perfectly fine and has no impact on the performance. The protection cuts, in this incarnation, the D23/D24 zenners current feed, shutting down the folded cascode gain stage. Also, no special soft clipping circuitry, the amp sticks for well under 1uS.
- 15ppm THD20 (0.0015%) at 160W output into 8ohm
- 18ppm THD20 (0.0018%) at 320W output into 4ohm
- IMD 19+20KHz is around 20ppm (0.0020%)
- 110V/uS slew rate, 800nS rise time for +/-50V output, defined by the input filter. Yes, the input filter is dampening the overshoot
.
- Output spectra shows mainly 2nd harmonic with some 3rd residual.
- Closed loop gain = 28
- 80 degree phase margin
- 0.01 degree closed loop phase shift
- Stable in whatever (capacitive) load I was able to provide.
Current feedback output stage with local loop. Low bias input stage, folded cascode gain stage, EF driver, 4 pairs of 2SK1530/2SJ162, two pole frequency compensation. Gain is set to 11, input stage is a THS4031 opamp, swinging about +/-5V, global gain is set to 28. Other +/-15V high speed opamps can be used, in fact it worked fine with almost any high speed unity gain stable opamp I was able to test. Using a low bias/low offset part guarantees a low output offset, no servo is required as in YAP. Only the EF drivers need on board heatsinks.
Costruction is a single board with local supply filtering 4x10,000uF/80V, board bolted to the 11"x5", 0.4C/W, heatsink, pretty much like the YAP output stage. Nothing really special regarding the PCB layout, this is not an ultra high ULG as YAP. Preliminary, I have connected two 1KW toroids, providing +/-72Vac, and the thing delivers (short time) 600W into a 2ohm load with 30ppm THD20. Not that I really need that kind of power, just making sure that the VSOP is going to drive even the most difficult 4ohm reactive loads without much of a problem.
I'll be back with further pictures, graphs, details, etc... meantime comments are welcomed.
But before that, here's an HPS update: National Semiconductor is now manufacturing LME49610, a high current (250mA) buffer, also supporting +/-22V. This, in combination with the relatively new LME49860 dual opamp, also supporting +/-22V, allows simplifying the power supply, without any sacrifice in headroom. Noise performance is of course the same... Details to follow soon!
I was looking for some time to further develop an as much as possible simpler power amp, preferable with a higher power spec (compared to PGP and YAP), without compromising to much the performance. The new schematic is attached. I'm currently feeding this new design with +/-60V (that's how much I can get from my 2 x 600W lab supplies), plan is to go up to +/-70V. Here are some key measured specs of the new VSOP (Very Simple Output Powerstage) amp. Pretty good for 12 small signal trannies, plus the output devices, and an opamp. No overcurrent protection, not sure if all that extra circuitry required to make the amp fool proof is really required, anyway the YAP "hifi thyristor" circuit works perfectly fine and has no impact on the performance. The protection cuts, in this incarnation, the D23/D24 zenners current feed, shutting down the folded cascode gain stage. Also, no special soft clipping circuitry, the amp sticks for well under 1uS.
- 15ppm THD20 (0.0015%) at 160W output into 8ohm
- 18ppm THD20 (0.0018%) at 320W output into 4ohm
- IMD 19+20KHz is around 20ppm (0.0020%)
- 110V/uS slew rate, 800nS rise time for +/-50V output, defined by the input filter. Yes, the input filter is dampening the overshoot
.- Output spectra shows mainly 2nd harmonic with some 3rd residual.
- Closed loop gain = 28
- 80 degree phase margin
- 0.01 degree closed loop phase shift
- Stable in whatever (capacitive) load I was able to provide.
Current feedback output stage with local loop. Low bias input stage, folded cascode gain stage, EF driver, 4 pairs of 2SK1530/2SJ162, two pole frequency compensation. Gain is set to 11, input stage is a THS4031 opamp, swinging about +/-5V, global gain is set to 28. Other +/-15V high speed opamps can be used, in fact it worked fine with almost any high speed unity gain stable opamp I was able to test. Using a low bias/low offset part guarantees a low output offset, no servo is required as in YAP. Only the EF drivers need on board heatsinks.
Costruction is a single board with local supply filtering 4x10,000uF/80V, board bolted to the 11"x5", 0.4C/W, heatsink, pretty much like the YAP output stage. Nothing really special regarding the PCB layout, this is not an ultra high ULG as YAP. Preliminary, I have connected two 1KW toroids, providing +/-72Vac, and the thing delivers (short time) 600W into a 2ohm load with 30ppm THD20. Not that I really need that kind of power, just making sure that the VSOP is going to drive even the most difficult 4ohm reactive loads without much of a problem.
I'll be back with further pictures, graphs, details, etc... meantime comments are welcomed.
An externally hosted image should be here but it was not working when we last tested it.
syn08 said:
Those are not filtering caps, ever heard about parasitic inductances and decoupling?
Now, if you can come up with a simpler design while keeping the same performance spec, I'm all ears
A good amp doesnt need all that decoupling.
To me it looks like someone just kept throwing transistors at the design until no more would stick !
nigelwright7557 said:
Yep, I used my favorite pitchfork for that
May I suggest this design that I'm sure you will appreciate for its simplicity, performance and, above all, amazing sound?
http://www.diyaudio.com/forums/showthread.php?postid=488194#post488194
syn08 said:
Yep, I used my favorite pitchfork for that
May I suggest this design that I'm sure you will appreciate for its simplicity, performance and, above all, amazing sound?
http://www.diyaudio.com/forums/showthread.php?postid=488194#post488194
I have built 3 high power amps for my disco and for playing guitar through.
They all had a LTP front end with the LTP served with a CCS.
The LTP fed into a VAS again with a CCS.
The bias was a Vbe multiplier of which each side feeds into 3 vertical MOSFETs.
Its by far not an ideal solution but it works and sounds good.
Sorry I cant supply a cct diagram as my CAD software doesnt have an export facility.
I think he's seeing the triple cascode (with the last one folded) and an emitter follower to boot being overkill. Maybe, maybe not.
It does take a minimum two stages in between the output followers and the opamp if you want nested current feedback. If .01% THD is all you want, that's all you need. (You won't even need the local loop.) If you're building a PA amp with 20 output trannies the layout will limit you to that anyway regardless of OLG. I've found that I at least like the Vas to be some sort of compound (darlington or cascode), even with those limits so that's 3 stages instead of 4. Whoopee. Saving 2 small signal trannies is nothing when you start adding up all the outputs.
To get distortion in the ppm range, the circuit itself is only part of the battle.
It does take a minimum two stages in between the output followers and the opamp if you want nested current feedback. If .01% THD is all you want, that's all you need. (You won't even need the local loop.) If you're building a PA amp with 20 output trannies the layout will limit you to that anyway regardless of OLG. I've found that I at least like the Vas to be some sort of compound (darlington or cascode), even with those limits so that's 3 stages instead of 4. Whoopee. Saving 2 small signal trannies is nothing when you start adding up all the outputs.
To get distortion in the ppm range, the circuit itself is only part of the battle.
Hi Ovidiu,
I noticed the gate resistors for the output devices are pretty large. Was this necessary for stability or were you just being conservative here?
Also, what's your take regarding the position of the gate protection zeners? I've considered putting them in the location shown in your schematic, but also worried that their max current isn't limited in that configuration. I've also seen (in Hafler designs) their cathodes hooked up to the the driver bases so the max current is limited by that of the VAS. OTOH, I guess one would not see them turn on even with a shorted output - only the case of parasitic oscillation of the output devices I suppose. So maybe it doesn't matter.
I noticed the gate resistors for the output devices are pretty large. Was this necessary for stability or were you just being conservative here?
Also, what's your take regarding the position of the gate protection zeners? I've considered putting them in the location shown in your schematic, but also worried that their max current isn't limited in that configuration. I've also seen (in Hafler designs) their cathodes hooked up to the the driver bases so the max current is limited by that of the VAS. OTOH, I guess one would not see them turn on even with a shorted output - only the case of parasitic oscillation of the output devices I suppose. So maybe it doesn't matter.
andy_c said:
Yes, they are conservative values. I may further tweak them, but there's no plan to push the ULG up, as for the YAP amp, at least in the first version. High ULG PCBs are barely available for the regular DIYer, the ultimate plan is to build VSOP on a single sided PCB.
Zeners have an interesting intrinsic property: they always get shorted, never open (and that's because the dynamic resistence at hih currents is usually smaller than the internal wiring, therefore the silicon melts first. OTOH, they always work in some sort of current limited environment, usually less than it takes to melt the internal wiring anyway. So I think connecting the zeners as close as possible to the MOSFET gates is better in terms of protection. The Hafler connection exposes the gates to drivers failures and, after all, worst case, who cares if the zeners die, they cost pennies anyway. Of course, ideally zeners should be connected directly to the gate of MOSFETS, but I think the advantage would be very small to pay for the board space required to accomodate 16 (for VSOP) DO-35 or DO-41 cases.
Michael Chua said:Hi syn08
Thank you for sharing your very interesting design.
May I ask what is the Full Power Bandwidth into 8 and 4 ohms. Is the Current Feedback path R93, R92?
By the way, the de-coupling caps for every power mosfets reminds me of Goldmund amps
Regards
Mike
Not sure what you mean by full power bandwidth, but the -3dB closed loop bandwidth is around 400KHz. It does not depend on the load.
The base amp is a current feedback configuration, with the inverting input at the Q61/Q62 bases and the non-inverting input at the R27/R28 junction, connected to the opamp output.
Hmmm, ya know that 2SJ78 and 2SK216 are available again.
I know it's kind of hard to do with multiple output devices -- but I found that initially using a 1K trimmer as the gate stopper, stressing the amplifier and adjusting for lowest THD% had a practical effect. Just measure the resistance and insert fixed values -- this was described by Troy Huebner in a nat semi ap note and it really does work. Perhaps you have to make a critical leap of faith to assume that all of the Ciss are the same, and just perform the experiment with one output device within the realm of SOA, etc., etc.
I know it's kind of hard to do with multiple output devices -- but I found that initially using a 1K trimmer as the gate stopper, stressing the amplifier and adjusting for lowest THD% had a practical effect. Just measure the resistance and insert fixed values -- this was described by Troy Huebner in a nat semi ap note and it really does work. Perhaps you have to make a critical leap of faith to assume that all of the Ciss are the same, and just perform the experiment with one output device within the realm of SOA, etc., etc.
I have a small stock of 2SK216/2SJ78, keeping them for a headphone amp when time will come. Not much use for power amps... My experience in using them as VAS, EF stage or drivers was always very poor in terms of distortions. They have way to much nonlinear capacitance compared to low Cob medium power bipolars.
Certainly, the gate resistors are very conservative. YAP uses 150/100ohm, but then again, these values allow a very high ULG, which is beyond the purpose of this design. Very high ULG like in YAP (8MHz) imposes very tough conditions on PCB layout and manufacturing, usually beyond what a DIYer can do at home. If I remeber correctly, VSOP has an ULG of around 1.5-2MHz which is pretty common. But I'll further experiment, before finalizing the PCB layout, and report here.
BTW, this design works great with 2SK1058/2SJ162 laterals, allowing further simplification (no bias thermal compensation required). These require larger gate stoppers (470/220 ohm is about right) but minimum 6-7 pairs for the same output power. To much in practice. For small powers up to 100W into 8ohm I've tried with excellent results 3 pairs of 2SK1058/2SJ162! This makes for only 10 small signal trannies and the board is further simplified (no need to place components on the heatsink, other than the output power devices).
Certainly, the gate resistors are very conservative. YAP uses 150/100ohm, but then again, these values allow a very high ULG, which is beyond the purpose of this design. Very high ULG like in YAP (8MHz) imposes very tough conditions on PCB layout and manufacturing, usually beyond what a DIYer can do at home. If I remeber correctly, VSOP has an ULG of around 1.5-2MHz which is pretty common. But I'll further experiment, before finalizing the PCB layout, and report here.
BTW, this design works great with 2SK1058/2SJ162 laterals, allowing further simplification (no bias thermal compensation required). These require larger gate stoppers (470/220 ohm is about right) but minimum 6-7 pairs for the same output power. To much in practice. For small powers up to 100W into 8ohm I've tried with excellent results 3 pairs of 2SK1058/2SJ162! This makes for only 10 small signal trannies and the board is further simplified (no need to place components on the heatsink, other than the output power devices).
I really like this amp, I was a little scared of the YAP..
I've heard the folded design before (roenders amp) but this
is symmetrical (I like).
would these be enough to power it ?
(2 X 1.8kva 53-0-53)
I also dug up 160K uf @ 100v.
About the 1530/ 201's are they vertical ? I have a pile
of IRFP 240's/9240's (free)
OS
I've heard the folded design before (roenders amp) but this
is symmetrical (I like).
would these be enough to power it ?
An externally hosted image should be here but it was not working when we last tested it.
(2 X 1.8kva 53-0-53)
I also dug up 160K uf @ 100v.
About the 1530/ 201's are they vertical ? I have a pile
of IRFP 240's/9240's (free)
OS
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