Might be wise to let TI worry about the stability of the preregulator(s) as indeed they already have, and focus your finite resources and finite design-man-hours upon the final regulator instead. BTW the fact that the model they supply to non-TI-TINA-software users, explicitly includes the word "transient", may suggest that it's a lot more trustworthy for .TRAN analysis than for .AC analysis. So hit it with a few sinewave inputs in a transient simulation and verify that the output sinewave is 75 dB smaller than the input sinewave.
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Makes sense. At the moment I am worried the Sziklai side of things won't start up when its op amp is powered from Vout. Modelled without the LM2941 in place it does, but when Vin to the D45VH10 pass transistor is the output of the LM2941 it doesn't. (Powered from Vin it takes a full 4-5 seconds to reach target output voltage, but this I see is just a result of the heavy filtering - 3.3k Ohms + 220u - of Vref I have in place, also taken from Vout, and I'm less worried about.)
EDIT: Can I ask a general question about testing the line rejection of a regulator circuit? When coupled to a transformer the left side of which is connected to the mains, we can look at the output of the regulator with an FFT and see how well it does at rejecting the 2x50/60Hz ripple. Presumably we could add test points on the board between the transformer and rectifier at which we could inject the secondary voltage at other frequencies of interest, examining the output of the regulator for each input and building a picture of the circuit's overall line rejection. Is this feasible? An issue would be getting a signal generator capable of a big enough output amplitude (mine is limited to 10Vpp) or an amplifier at the input would be required, but I am wondering if the principle is sensible. Of course, if the line rejection is exceedingly good then a very good amplifier will be needed at the output also. (I have built Samuel Groner's measurement amplifier so this I have.)
EDIT: Can I ask a general question about testing the line rejection of a regulator circuit? When coupled to a transformer the left side of which is connected to the mains, we can look at the output of the regulator with an FFT and see how well it does at rejecting the 2x50/60Hz ripple. Presumably we could add test points on the board between the transformer and rectifier at which we could inject the secondary voltage at other frequencies of interest, examining the output of the regulator for each input and building a picture of the circuit's overall line rejection. Is this feasible? An issue would be getting a signal generator capable of a big enough output amplitude (mine is limited to 10Vpp) or an amplifier at the input would be required, but I am wondering if the principle is sensible. Of course, if the line rejection is exceedingly good then a very good amplifier will be needed at the output also. (I have built Samuel Groner's measurement amplifier so this I have.)
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That sounds reasonable. I have heard that Douglas Self wrote an article showing measurement results from injecting periodic test signals into various places inside power supplies, but I haven't seen the article or a proper bibliographic reference for it.
Naturally you could connect the secondary of a 1:1 transformer in series with the AC mains, and then drive the primary with an audio power amplifier. (Mind the load impedance!). Presto, any waveform you want, superimposed upon 230VAC 50Hz.
Naturally you could connect the secondary of a 1:1 transformer in series with the AC mains, and then drive the primary with an audio power amplifier. (Mind the load impedance!). Presto, any waveform you want, superimposed upon 230VAC 50Hz.
Thanks.
OK I now have the "LM2941 + Sziklai from Vout" sim working. It required a larger cap between the LM2941 pre-reg and the Sziklai reg. AC analysis looks way off with no contribution to line rejection at low frequencies from the LM2941 (I will look at this a little more), but .tran seems to work to allow observations in the time domain.
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I'll add this circuit to the new thread I created as well. Not sure the "bi-directional drive" is worth further pursuit. I certainly couldn't seem to model it in a way that lead to improvement.
OK I now have the "LM2941 + Sziklai from Vout" sim working. It required a larger cap between the LM2941 pre-reg and the Sziklai reg. AC analysis looks way off with no contribution to line rejection at low frequencies from the LM2941 (I will look at this a little more), but .tran seems to work to allow observations in the time domain.
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- Circuit
- Output
- Closer look at transient, load 0.25A->0.5A
- Closer look at transient, load 0.5A->0.25A
- Line rejection analysis not working
I'll add this circuit to the new thread I created as well. Not sure the "bi-directional drive" is worth further pursuit. I certainly couldn't seem to model it in a way that lead to improvement.
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Superimpose a 2 volt amplitude 10 Hz sinewave upon the raw DC input V1 and see what amplitude you get at the output pin of the LM2941 in transient analysis. You expect to get an 0.36 millivolt output from a 2 volt input (-75 dB).
Then I suggest you hang your head in shame about J1+R6. Go back and look in your project notebook for the day and time when you decided upon that circuit and those component values. Revisit your calculations, look again at your current-source-ed-ness plot of (Vacross) versus (Ithrough). An ideal current source is a horizontal line, I=constant, for any and all voltages across it. How ideal is J1+R6?
Then I suggest you hang your head in shame about J1+R6. Go back and look in your project notebook for the day and time when you decided upon that circuit and those component values. Revisit your calculations, look again at your current-source-ed-ness plot of (Vacross) versus (Ithrough). An ideal current source is a horizontal line, I=constant, for any and all voltages across it. How ideal is J1+R6?
Oh indeed. No idea what happened there. Looks like I started to change things and then was interrupted or something.
Now changed to J109, gate to ground and looks like a resistor of about 487 Ohms models 10mA of current sink. The BC807-40 PNP transistors in the current mirror feed current to the base of the driver MMBT6429 and on through to the output of the regulator. I've been trying to digest the discussion on pg 503 of Art of Electronics 3rd ed. together with the table on pg 501 to see if it is worth changing these parts in the actual design. Thoughts?
I'll now look at your suggestion in your first paragraph above.
I can see in posts135 & 140 that the gain curve steepens at just under 100kHz but BEFORE the gain has dropped to +0dB.
That massively reduces the phase margin.
It plummets to 36degrees @ 0dB whereas 38kHz (before the kink in the gain plot) where gain is ~+38dB the phase margin is still up around 80degrees.
Do you need to move that steepening kink further to the right so that the gain plot passes through 0dB while the slope is still on the less steep side of the kink?
There is a further steepening kink @ ~2MHz. It does not matter to phase margin if both kinks are around that 2MHz. They would both be above the 0dB frequency.
That massively reduces the phase margin.
It plummets to 36degrees @ 0dB whereas 38kHz (before the kink in the gain plot) where gain is ~+38dB the phase margin is still up around 80degrees.
Do you need to move that steepening kink further to the right so that the gain plot passes through 0dB while the slope is still on the less steep side of the kink?
There is a further steepening kink @ ~2MHz. It does not matter to phase margin if both kinks are around that 2MHz. They would both be above the 0dB frequency.
As Mark notes, a phase margin of 36 degrees isn't an unstable circuit. However, it is less headroom for the inevitable parasitic poles that aren't modelled. Hence the 'rule of thumb' of 45 degrees of margin - it's only a rule of thumb.
When you look at the phase and gain profile of Mark's circuit it's not surprising that the output cap ESR is so important for the LM2941.
If you have ideas as to how to improve phase margin with minimal impact to circuit performance by all means toss them out. If you would like to play around with the LTspice model I will gladly post it. The usual tactic of adding a small cap to allow high frequencies to skirt around the op amp has the opposite affect - it reduces phase margin. Perhaps HF need to skirt around the JFET driver. I haven't thought about it / played with it enough yet.
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Naaah, it's just the LCT1150 itself. The brain trust at Linear Technology reasoned, quite properly, that nobody in their right mind is going to pay $7.50 for a zero-drift opamp whose open loop gain is one billion (180 dB) and whose PSRR is 145dB, and then operate the damn thing at unity gain! So they opened up the bandwidth juuuust enough to make it barely stable at unity gain. Then they added this pin-1 business {found in the datasheet but NOT in the LTSPICE simulation model} which reduces GBW at low frequencies and improves phase margin at 800 kHz. Take a look at the datasheet figures:
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With the MOSFET pass transistor design it was necessary to protect the MOSFET by using a Zener diode to prevent Vgs being exceeded. I note that the Jung/Didden super regulator doesn't require protection of the BJT pass transistor. Before I play around with board layouts, I wonder if I am missing any protection elements in the circuit below.
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If there's room why not put a multiturn trimmer in series with R31 and R33? You can tweak the preregulator's output up and down a little bit, to fine tune the division-of-labor between the preregulator and the final regulator as far as power dissipation is concerned.
Attached is a fragment of a schematic from an old Tektronix product, the PS501 power supply. I've marked a component with a red arrow. Maybe it's a good safe play to lay out this resistor on your board; it it turns out not to be needed, a zero ohm resistor or a jumper wire can be stuffed and soldered.
Attached is a fragment of a schematic from an old Tektronix product, the PS501 power supply. I've marked a component with a red arrow. Maybe it's a good safe play to lay out this resistor on your board; it it turns out not to be needed, a zero ohm resistor or a jumper wire can be stuffed and soldered.
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Thanks. Perhaps something like this 5K SMD trimmer in the upper half of the voltage divider. If R32 is 1K that would give an output range of 6.4 volts within 5 turns of the trimmer. With slightly long traces I can squeeze it onto the top side of this board which is rather cramped.
I added R37/38. Isn't 51 Ohms as a base stopper rather large?
I've done a first cut of one half of this board (V+). I will finish laying it out, but I think I will do a version without the PCB transformer for testing first. The PCB transformers are only 10VA (5VA per secondary pair) and so current capability is modest. It is probably even better to test with a simple V+ only board but if it works well I'd rather have the dual supply to put to immediate use.
I added R37/38. Isn't 51 Ohms as a base stopper rather large?
I've done a first cut of one half of this board (V+). I will finish laying it out, but I think I will do a version without the PCB transformer for testing first. The PCB transformers are only 10VA (5VA per secondary pair) and so current capability is modest. It is probably even better to test with a simple V+ only board but if it works well I'd rather have the dual supply to put to immediate use.
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Now that you've got a preregulator you can consider interchanging R11 and J1; i.e., allowing the PNP current source(s) to depend upon the DC value of the preregulator output (which is -75dB uber stable), while getting another 40dB of load regulation by increasing the impedance between VREF and VREGout. Just plain old common sense.
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I'm not sure I understand you correctly. I see that now there's a pre-regulator supplying Vref from a mirror if the J1/R21 current source frees it from load fluctuations and improves the circuit load regulation (although presumably C17 provides a partial buffer to these fluctuations). Or even more simply, shift R11 to the input side of Q7 although presumably the former, while requiring 1 or 2 more parts, would be better. Is this what you mean? Or do you mean to go further still and just programme the current mirror with a resistor rather than n-channel JFET?
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Ok understood. I guess another option, if it fits, would be to just add another nJFET ahead of R11 (tying its gate to the low side of R11).
How did you calculate 40dB? I've been trying to figure out how to model load regulation in LTspice. I was thinking I could just add a small signal AC to the load and conduct an AC analysis, but it doesn't seem to work.
How did you calculate 40dB? I've been trying to figure out how to model load regulation in LTspice. I was thinking I could just add a small signal AC to the load and conduct an AC analysis, but it doesn't seem to work.
The incremental, small signal model of the VREF generator (pullup resistor + LM329 superzener), neglecting the subsequent RC filter which does not work all the way down to DC, is just a voltage divider. Its transfer function (vout/vin) is simply the transfer function of a voltage divider, namely
In the BEFORE picture the "pullup impedance" is R11 which I am guessing you will choose to be around 1K to give 5mA of current in the LM329. In the AFTER picture the "pullup impedance" is the output impedance of the current source, which I am guessing you will be able to achieve 100K at the very least.
Voila, the small signal transfer function (v_ref / v_regulator_output) falls by a factor of 100X which is 40dB. At DC.
- (v_ref / v_regulatoroutput) = lm329_impedance / (lm329_impedance + pullup impedance)
Voila, the small signal transfer function (v_ref / v_regulator_output) falls by a factor of 100X which is 40dB. At DC.
Most places define Load Regulation to be deltaVout/deltaIout , which is identical to the definition of output impedance. To measure it, attach a load resistor between voltage regulator output and ground, chosen so its current is ~ 25% of max allowed output current. Then run an AC analysis where you inject a current source (DC=0, AC=1) into the output pin, and plot Z = Vout/Iinject versus frequency.
The old old voltage regulator datasheets treated Load Regulation as a DC specification: what is the change in Vout, between Iout=25% of max and Iout=75% of max? Clearly the way to win that ancient specsmanship war is to use the LTC1150 with 180dB of gain at DC. Then Load Regulation = Zout = (1/gm)*((Rtop+Rbot)/Rbot)*1E-9 where gm is the transconductance of your series pass transistor network at 25% of max Iout. But this is stupid because the load current in real life does in fact contain other frequency components besides DC, and so Zout vs frequency tells you more about what can happen in real life.
The old old voltage regulator datasheets treated Load Regulation as a DC specification: what is the change in Vout, between Iout=25% of max and Iout=75% of max? Clearly the way to win that ancient specsmanship war is to use the LTC1150 with 180dB of gain at DC. Then Load Regulation = Zout = (1/gm)*((Rtop+Rbot)/Rbot)*1E-9 where gm is the transconductance of your series pass transistor network at 25% of max Iout. But this is stupid because the load current in real life does in fact contain other frequency components besides DC, and so Zout vs frequency tells you more about what can happen in real life.
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