Linear Technology's Remote Sensing circuit in post #179 above, is somewhat unusual. I've copied the schematic below and added names for each of the components. Readers may enjoy discovering whether or not it works, and if so, how? It's a fun little problem in circuit analysis.
I've attached my own analysis and explanation below. It's in a .zip archive file so it won't accidentally pop up when you're browsing this thread, and ruin the surprise / fun of deconstructing the circuit. More than one "click" are required to open the zip archive, you can't do it by accident. Neither can your cat, no matter how furiously she pats your keyboard or touch screen.
I've attached my own analysis and explanation below. It's in a .zip archive file so it won't accidentally pop up when you're browsing this thread, and ruin the surprise / fun of deconstructing the circuit. More than one "click" are required to open the zip archive, you can't do it by accident. Neither can your cat, no matter how furiously she pats your keyboard or touch screen.
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As I was looking at the rather poor transient response of a dual LT1084 regulator I was thinking about this post. I would have readily to hand a rather good 12V supply (assuming the whole construction works). It would be easy to run a couple of pairs of wires, one to the 5V board and another to the 3V3 board. A couple of strategically positioned solder pads (unused on the 12V board) would allow landing of the 12V on the other 2 boards. A large number of components on the 5V and 3V3 boards would not need to be populated. A well-placed 0 Ohm resistor would allow by-passing of unpopulated level shift components. I think Vgate only needs to be c3V above Vout. The AD797 with 12V supply might even swing high enough for 5V out...
Am I going mad?
The "Supervoltage Input" option simplifies your life BUT it drastically reduces the circuit's appeal to other people. Who else might possibly want to build your 3.3V regulator board which, oh by the way, also requires a well regulated 12VDC input? If one of your goals is to be the famous designer of a much-loved and frequently built DIY project, the supervoltage idea may wreck your plans.
It seems to me that a quick .DC simulation of a load resistor, series pass transistor, +12VDC supply, and 100% perfect, error-free, and approximation-free AD797 opamp spice model .... could answer the question: Can an AD797 running on 12VDC, drive the gate of a series pass transistor (without level shifter) to produce 5V output at max possible current?
If the answer is no, you could of course apply the higher voltage but greater ripple, unregulated input which drives your 12V regulator board.
It seems to me that a quick .DC simulation of a load resistor, series pass transistor, +12VDC supply, and 100% perfect, error-free, and approximation-free AD797 opamp spice model .... could answer the question: Can an AD797 running on 12VDC, drive the gate of a series pass transistor (without level shifter) to produce 5V output at max possible current?
If the answer is no, you could of course apply the higher voltage but greater ripple, unregulated input which drives your 12V regulator board.
Oh, I have no desire for fame and I could not claim credit for the reg circuit anyway. I have, however, added to my 'to do' list to at least lay out this circuit as a little DC regulator board at perhaps lower current spec so as to reduce heatsink requirements. Perhaps that might be of more interest to others.
I had already started testing "The AD797 with 12V supply might even swing high enough for 5V out..." A little over 9V is required and so 12V would seem to provide good headroom.
I had already started testing "The AD797 with 12V supply might even swing high enough for 5V out..." A little over 9V is required and so 12V would seem to provide good headroom.
Hi Luca, yes there is. I didn't want my opinions to pollute anyone else's thinking about the circuit. I'll post the password in a week or so, after people have had time to think about the circuit or ignore the circuit. If you cannot possibly wait that long, send me a PM.
Not much progress due to alternate demands on my time and some LTspice issues. I did finish linking the 3 regs in LTspice and - apologies to Elvee - I am finally posting the .asc files.
Strangely, powering the Vref for the 5V and 3V3 rail from 12Vout affects the modelled PSRR of Vref for the 12V reg (with subsequent deterioration in 12Vout PSRR which likely affects the other voltages). This makes no sense to me as 12Vref is driven from Pre12Vreg and not 12Vout.
Attached zip of necessary .asc files etc and some pics of modeled PSRR.
Strangely, powering the Vref for the 5V and 3V3 rail from 12Vout affects the modelled PSRR of Vref for the 12V reg (with subsequent deterioration in 12Vout PSRR which likely affects the other voltages). This makes no sense to me as 12Vref is driven from Pre12Vreg and not 12Vout.
Attached zip of necessary .asc files etc and some pics of modeled PSRR.
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Mark or others, do you have any views on a Zoebel network in lieu of a gatestopper resistor. Cordell mentions a 47 Ohm resistor in series with a 100pF capacitor from gate to drain as being a better solution to potential instability than a gatestopper. In line with his comments, it would appear to provide more phase headroom with less impact on PSRR (less impairment of the speed of the pass transistor).
Attached are modeled phase and gain margin (0.1A load) with a 100R gatestopper which also requires heavier op amp compensation. Also attached is the same for the Zoebel network; it would appear to provide more phase cushion albeit less gain margin, allows less heavy compensation and models better PSRR.
Thoughts?
Attached are modeled phase and gain margin (0.1A load) with a 100R gatestopper which also requires heavier op amp compensation. Also attached is the same for the Zoebel network; it would appear to provide more phase cushion albeit less gain margin, allows less heavy compensation and models better PSRR.
Thoughts?
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The safe play is to include all three components in the schematic and (more importantly) on the PCB. If you think you prefer the RC network from gate to drain, go ahead and include an 0.10 ohm gatestopper resistor too. Now you can try out one approach (gatestopper but no RC) and/or the other approach (RC but no gatestopper) without fabbing new PCBoards.
Latest and greatest. I still have some modelling to do here. Looks like R1 and R2 won't be needed, but I am not sure it's worth redoing the board as the space freed up largely ends up falling between C3 and C4. I may just dump the LED1/R14 indicator.
Schematic with annotations, board and BoM attached. All comments/advice greatly welcomed!
[Thinking about soldering the 12V SMD parts is intimidating. (The other rails should be easier as they omit many of the parts.) I will print the board actual size on a sheet of clear film and cut a stencil. I'll then have a go at 'skillet reflow soldering' it. I have an induction hob with a metal plate that converts it to a regular hob. The temp of this can be set. Unless of course there's a real risk that the induction will destroy parts?]
Schematic with annotations, board and BoM attached. All comments/advice greatly welcomed!
[Thinking about soldering the 12V SMD parts is intimidating. (The other rails should be easier as they omit many of the parts.) I will print the board actual size on a sheet of clear film and cut a stencil. I'll then have a go at 'skillet reflow soldering' it. I have an induction hob with a metal plate that converts it to a regular hob. The temp of this can be set. Unless of course there's a real risk that the induction will destroy parts?]
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Load capacitance.
I'm getting unstuck when I add load capacitance to my regulator circuit.
When I model the stability of the regulator circuit itself including its two output caps I get good phase margin (c80 degrees for example) and decent gain margin (23dB @ 0.1A load, 13dB @ 5A load). However, if I tack onto the model a capacitor to represent load capacitance (e.g. the 8,000uF mentioned in the ATX Power Supply Guide for 12V load capacitance) everything goes to hell in a hand basket.
The 8,000u may well be very conservative, who knows. There will also be some ESR. My question is whether it is right to model this capacitance. Surely not every regulator circuit devised knows the load capacitance to which it will be attached.
Or is this merely, as I currently fear, a sign of a bad circuit - one intolerable of load capacitance and likely unstable in practice.
I'm getting unstuck when I add load capacitance to my regulator circuit.
When I model the stability of the regulator circuit itself including its two output caps I get good phase margin (c80 degrees for example) and decent gain margin (23dB @ 0.1A load, 13dB @ 5A load). However, if I tack onto the model a capacitor to represent load capacitance (e.g. the 8,000uF mentioned in the ATX Power Supply Guide for 12V load capacitance) everything goes to hell in a hand basket.
The 8,000u may well be very conservative, who knows. There will also be some ESR. My question is whether it is right to model this capacitance. Surely not every regulator circuit devised knows the load capacitance to which it will be attached.
Or is this merely, as I currently fear, a sign of a bad circuit - one intolerable of load capacitance and likely unstable in practice.
Rather late in the game to be discovering a potentially fatal problem!
It might be reassuring / it might be terribly frightening, to do a few simulations that estimate the number "X" in the homework problem below.
It might be reassuring / it might be terribly frightening, to do a few simulations that estimate the number "X" in the homework problem below.
What is the minimum length "X" of a twisted pair of copper wires, #16 AWG wires (1.29mm diameter), such that a twisted pair X or longer between the regulator and the load, gives adequate stability? However you choose to define adequate? Don't neglect the resistance per unit length, inductance per unit length, or capacitance per unit length, of a twisted pair of #16 AWG copper wires.
Of course if you have a solid reason why this exercise is obviously a waste of time, then don't waste time on it. And if you have an airtight reason to study a different wire diameter, nobody here can stop you.
It was a very disconcerting afternoon as I added series resistance and self-inductance for 30cm of 14AG wire (that's what I have although I find it difficult to work with), looked repeatedly at the depressing outcome (aka worse) and futsed around until, and only after typing a response here and almost hitting send, I finally read your post once more and realised that I hadn't added the resistance and inductance to the return wire of the twisted pair! What a difference after that lead penny clanged on the floor... Thanks!!
Oh and I needn't have really put the load capacitance into my AC-voltage-driven 'observe in-rush and power dissipation' model in the first place as it sits behind the 'power control board' pass transistors and isn't charged until PWR-ON is received, well after the initial in-rush to charge the PSU filter caps. It is of course relevant to the control board pass transistors' SOA.
(BTW I did look at a simulation using the LT1498 rather than the AD797A. It does indeed perform very well, albeit not quite as well as the AD797A. Quite likely a good choice for a low voltage stand-alone circuit.)
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Hopefully I am getting near to the point of ordering boards and parts (including at least the heat sink part of the enclosure). I never got an answer from Wurth re the ferrite beads and have limited space for them on the board. I will use a filtered IEC inlet and leave it at that for now.
One thing I am wondering about is bleeding the filter caps. AndrewT at one point, if I recall correctly, said he doesn't like using them. Yet it would seem to me wise not to leave large caps charged. The indicator LED will bleed the smaller output caps but at some point the pass transistor will turn off leaving charge in the main filter caps. Is it recommended to add a bleeder resistor after the 3 large input caps?
(If "yes" any guidance as to size/bleed current to alleviate the concern I think AndrewT expressed?)
One thing I am wondering about is bleeding the filter caps. AndrewT at one point, if I recall correctly, said he doesn't like using them. Yet it would seem to me wise not to leave large caps charged. The indicator LED will bleed the smaller output caps but at some point the pass transistor will turn off leaving charge in the main filter caps. Is it recommended to add a bleeder resistor after the 3 large input caps?
(If "yes" any guidance as to size/bleed current to alleviate the concern I think AndrewT expressed?)
I include bleeders myself. I choose the Yageo "skinny boy" resistors (1W @ 2.4mm x 6.3mm (link 1)) or else (2W @ 3.9mm x 9.0mm (link 2)). I select the resistance value such that the worst case max dissipation (no load on supply, mains +10%, diode Vfwd_min, etc) is half of the resistor wattage rating.
Why do I like bleeders? Because I've received a nasty shock when servicing equipment (designed by "the legendary Bob Carver") that omitted them.
I prefer to include explicit bleeder resistors even when power-is-good rail indicator LEDs are present. Dogma? Dogma.
Thanks Mark. I was thinking the same re potential shocks. I will make the changes.
I've been distracted by another thing I'm witnessing in LTspice. To check all my power dissipation, voltage headroom etc I have a circuit which includes the NTC-based soft start, toroid, rectifier diodes and, of course, the regulator. I have stripped this back to just the 12V rail and attached it here. See attached.
The sim shows Vref for the 12V rail taking a long time to come up to 6.9V which surprised me initially because it's not the case in the DC-driven circuits but I believe it's because C3 needs to be charged and the RC filter has a very long time constant of some 1.55s and so Vref takes 6+ seconds to come up to spec. I guess I have learnt that LTspice assumes everything is fully charged when using DC voltage sources? (And that on initial turn-on there will be quite a delay before PWR_OK is true.)
What's interesting is if I run the circuit plotting Vref with differing circuit loads. Zero load = almost instantaneous Vref. 100mA and I get the gradually increasing Vref similar to the graphic I attached. In all cases the current through R4 is relatively unchanged, the voltage potential on the left side of R4 is unchanged. The currents through D1 and R3 do change materially with load which doesn't make any sense to me given the level of current through the non-inverting pin of the op amp should be minuscule in all conditions. I guess this is just device sim inaccuracy. There's quite a difference in this behaviour if one uses the AD797 model rather than the AD797A with the former seemingly producing more realistic results (except for zero load)...
I've been distracted by another thing I'm witnessing in LTspice. To check all my power dissipation, voltage headroom etc I have a circuit which includes the NTC-based soft start, toroid, rectifier diodes and, of course, the regulator. I have stripped this back to just the 12V rail and attached it here. See attached.
The sim shows Vref for the 12V rail taking a long time to come up to 6.9V which surprised me initially because it's not the case in the DC-driven circuits but I believe it's because C3 needs to be charged and the RC filter has a very long time constant of some 1.55s and so Vref takes 6+ seconds to come up to spec. I guess I have learnt that LTspice assumes everything is fully charged when using DC voltage sources? (And that on initial turn-on there will be quite a delay before PWR_OK is true.)
What's interesting is if I run the circuit plotting Vref with differing circuit loads. Zero load = almost instantaneous Vref. 100mA and I get the gradually increasing Vref similar to the graphic I attached. In all cases the current through R4 is relatively unchanged, the voltage potential on the left side of R4 is unchanged. The currents through D1 and R3 do change materially with load which doesn't make any sense to me given the level of current through the non-inverting pin of the op amp should be minuscule in all conditions. I guess this is just device sim inaccuracy. There's quite a difference in this behaviour if one uses the AD797 model rather than the AD797A with the former seemingly producing more realistic results (except for zero load)...
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