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Old 6th September 2012, 10:50 AM   #1011
tsiros is offline tsiros  Greece
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Quote:
Originally Posted by gootee View Post
Here is an example of the power supply distortion that I am using to determine the "cutoff" point for the "minimum" required capacitance.
For amplifiers with respectable PSRR/CMRR, a small power supply ripple wouldn't affect it much, did you take that into consideration?
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Old 6th September 2012, 12:20 PM   #1012
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You have not read this Thread!
The output stage is being investigated.
The input stage is being treated as if it were perfect.
This is equivalent to saying that the PSRR is infinity and CMMR is minus infinity.

This Thread is not investigating the performance of a voltage amplifying stage. That should rightly be left to simulation of an amplifier.
This Thread is investigating the effect of PSU on the performance of the output stage.
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Old 6th September 2012, 04:45 PM   #1013
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It appears as if a conclusion and a rule of thumb is in the making!
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Old 6th September 2012, 05:03 PM   #1014
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Terry Given,
Any chance you could post a simple schematic or even better yet that and a sketch of the physical layout you would use for the multiple distributed capacitors in parallel with and without the CRC configuration. It's up to you but it would be greatly appreciated.I assume at some point there would still be a single film capacitor in parallel also?

Steven
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Old 6th September 2012, 05:56 PM   #1015
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Quote:
Originally Posted by Terry Given View Post
I've been looking at the SYMEF layout, and figuring out a nicer way to do it. conclusion: good layout is not easy to do - I'm not surprised so many amp layouts are so bad. I'm getting there (4 layers is OK, 2 layers is much harder), but I really dont like the air-core output inductor.
Hi Terry and fas, everyone Come on and show some team spirit by joining me here http://www.diyaudio.com/forums/group...p-thing-2.html. Yes Terry do show and tell.

Also I have wonderful PCBs for you to experience here http://www.diyaudio.com/forums/parts...available.html.

Using these we can be able to explore ground truths in relation to theory

Last edited by OnAudio; 6th September 2012 at 06:07 PM.
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Old 6th September 2012, 05:59 PM   #1016
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Steven,

yeah I will post my attempt at a layout when I'm done. but its really as simple as it sounds - two big flat plates, one 0V and the other V+ (or V-), on opposite sides of the PCB. the trick is quite simply to not chop great big holes/slots into either plate.

the inductance per unit length of a parallel plate transmission line w metres wide with a separation of s metres is u0*s/w [H/m], where u0 = 4*pi*10^-7 = permeability of free space. so for a 120mm width and 1mm separation, L = 10.5nH/m.

It makes sense to have the local cap bank as wide as the power stage - conversely its not a smart move to make it much wider, or narrower, than the power stage. if much wider the caps on the edges wont carry as much current (reductio ad absurdum - if its 10x wider than the power stage then they sure as heck wont do much). If the cap bank is much narrower than the power stage, then the transistors at either edge are too far away from the cap bank.

Likewise with the depth of the capacitor bank - the distance between the DC input and the power stage. Current from the DC input needs to "spread out" across the full width of the cap bank, before it gets to the power stage. If we imagine a cap bank that is a single row of caps deep (so as shallow as it can be), then the input current cant spread out (current spreading is a diffusion equation, exactly the same as heat spreading).

you really dont want to try and figure it out analytically (dyadic Green's functions & Schwarz-Christoffel transformations can ruin an otherwise good day), FEA is much friendlier (by which I mean less un-friendly). evil learning curve and $$$ for the really good SW though - but something 2D and free like FEMM can model a step-change in conductor width very easily.

Back in the real world, I'd make sure the cap bank is fairly square - or at least not too rectangular - and call it quits at that. Because I am assuming we're NOT designing for manufacture (IOW down to a price) here - if we were, then a full analysis/FEA would be used to determine the absolute minimum dimension & no of caps (and I'd get paid).


As far as paralleling film caps: the neat thing about a pair of parallel plates is they act as a free, zero-inductance capacitor. FR4 Er = 4.5, so the capacitance is about 40pF*Width*Depth/Spacing. for our hypothetical 120mm x 120mm 1mm PCB, thats 1/2nF. If I were to use a 4-layer PCB with a thick core and 0.13mm prepreg between TL & ML1 (and also ML2-BL) then that would be more like 4.5nF of extremely broad-band capacitance.

EL caps are in metal cans, so when you parallel them you can pretty much ignore mutual coupling. This means that the ESL really does go down in proportion to the no. of caps, as does ESR. But with leaded film caps, this is not the case - mutual coupling interferes with the reduction in ESL of paralleled caps. I measured the ESL of a panasonic ECQ-E 100nF 630V cap as 5.9nH. two in parallel gave 4nH - 30% more than you would expect. This was done with a network analyzer and special test PCBs, using full one-port calibration and custom calibration standards (same PCB & SMA interconnect). The PCBs were 1mm thick parallel-plate transmission lines, with an SMT SMA connector in the center, underneath the cap or caps (separate PCB for two caps in parallel).

So when you parallel a bunch of N x EL caps and do it properly, you really do get ESR/N and ESL/N - up to the point where the PCB itself dominates. eg our 100 x 1000uF caps - at ESL = 15nH this suggests 15nH/100 = 0.15nH. But the PCB is about 1nH, so after you have about 10 caps in parallel the overall DC bus inductance reduces much more slowly and eventually reaches a limit.

translation: a well-laid-out parallel cap bank is actually pretty darned good - enough that leaded film caps just wont help.

BUT smt caps probably would help. Never, ever use any dielectric "higher-K" than X7R - they all contain titanium baranate (IIRC) and are quite piezoelectric, along with horrendous boltage and temperature coefficients. I once replaced a 1206 1uF Z5U cap with a 1206 220nF X7R cap and tripled the amount of capacitance - there was 20V DC on a 25V cap and a wide temperature range. At Tmax the Z5U cap gave about 70nF (no, thats not a typo).

there are some quite nice smt film caps available. the inductance of an smt cap is governed almost entirely by its case size - a 1uF 0603 cap has the same ESL as a 10pF 0603 cap (about 0.8nH). So use the largest cap value you can get in a given footprint.

Alas vias also have inductance - about 1nH or so. So use 3 x 0V vias on the smt cap, close to the three visible edges of the pad (not enough room to put one under the cap).

[if you are crazy about low ESL, try mounting smt resistors upside down.....doesnt work for caps though)

HTH
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Old 6th September 2012, 06:38 PM   #1017
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Quote:
Originally Posted by gootee View Post
Also, I still say that the power and ground rails should be implemented using multiple separate parallel pairs of conductors, that stay separate all the way from the rectifier outputs to the load, with a separate capacitance for each end of each pair of power/ground conductors.
Without a sketch, I don't know what to make of it. However, that is obviously the answer to my parallel filters question, which was asked because the loss of series filters makes the transformer less effective. You've redeployed the cable runs that were already in place, used them parallel to make the ballast for faster charging (makes transformer more effective) and located capacitance closer to the load (makes capacitance more effective). Those steps appear to decrease the power supply reservoir size requirements somewhat. Even so, I can't quite get it in my head until I see it. I'm afraid I'd make a mess of it.
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Last edited by danielwritesbac; 6th September 2012 at 06:40 PM.
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Old 6th September 2012, 08:43 PM   #1018
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Daniel and HTH,
I am all for seeing the implementation of this parallel capacitor layout. Terry, most of what I think that you are talking about would require me to do a board layout following your recommendations. Now I am building one of OnAudio's IDIFFQC boards and so I can't implement this with his per-existing boards. So the idea of a multistrand wired circuit parallel to the boards is what I am wondering about. How to implement that is the question? I'm not sure that I can even do that with a board that wasn't planned this way to begin with. Perhaps there is a way to route the power rails around the rest of the circuit and still have a portion of the supply bypass the rest of the board and feed the output devices directly? I will wait to see a simple schematic and component layout and see if I can figure this out.

Steven
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Old 7th September 2012, 01:27 AM   #1019
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Steven (HTH = Hope That Helps),

Toms suggestion is, on the surface, something that could be done easily - at least it looks that way. In practice its just like my suggestions re. parallel planes - the PCB needs to be designed that way right from the outset. In either case its really important to get the layout and cabling right, lest you make things worse - using multiple cables provides lots of opportunities to get it really, really wrong unless you grok Toms concept (which is a good one), and the PCB layout isnt much better in that regard.

When you have an amp that doesnt have much local decoupling, you'll want to sit your cap bank nice and close - this maximises inductive coupling, so you must tightly twist/plait the xfmr leads (which will be fairly long). and likewise with the PSU to Amp Dc bus leads.

The advantage of a hefty bank of caps at the amp is that it allows you to move the main cap bank closer to the xfmr (shorter xfmr leads) and further from the amp (longer DC bus leads). all the wiring still must be tightly twisted though.

When you make your cap bank, use a DIY 2-sided PCB. Use DS Cu-clad PCB material, with one side 0V and the other side V+ (or V- or both). If you use leaded caps its not very hard - the top-side lead gets bent at right angles & trimmed, the other lead needs a hole. Then the cap is inserted, the top lead is soldered on and then the underside.

by doing one cap at a time you can get decent packing density and keep the caps nice and flush to the PCB, without having to pay for the fabrication of a DS-PTH PCB. Attached is a photo of one I prepared earlier, which has 24 x 270uF 100V KZE caps in parallel, giving 6.48mF. You can see how I've made the PCb is as outlined above.

I'll measure the DC bus impedance, along with the impedance of a 12mF 25V electrolytic (I dont have a 6.8mF cap handy). I need to wait for the network analyzer to warm up though.....
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Old 7th September 2012, 02:50 AM   #1020
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Terry,
So if I am following this correctly you have used a double sided board with solid cu planes on each side. I see the banks of capacitors, and I think that the diodes are hanging on the end and that is your bridge rectifier, next to that are the capacitor/resistor snubbers? What I am not sure about are the two devices that are closest to the capacitors? what are those? I get the idea you are presenting. I would think that the wires should probably be twisted tighter then I am seeing but that is about all. Thank you for showing this,

Steven
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