paralleling film caps with electrolytic caps

[ChocoHolic]

Originally posted by Conrad Hoffman
.... The numbers for PSRR have to be stretched to the breaking point to consider power supply caps part of the signal chain...

...yupp that's exactly why I am wondering when somebody tells me that the supply cap has a major influence on bass control. At these frequencies the PSSR of any normal power amp is 60db or higher (except class D !!!) .
And in fact I never observed any dominant low frequency artifacts of the rails in my output voltages.
May be we have to dig deeper. If there is a real corelation between supply caps and bass response, then it is not a very obvios one. The obvious straight forward effects are no issue IMHO. At least up to now all my measurements indicate close to perfect behavior in this regard. If all this is not a myth, then there must be a less obvios effect. I know that different bass sound & control is not a myth, even if you only change the amp and keep everything else the some. But I do not know if and how this is really caused by the rail caps.

Hm... may be we should open another thread for this.. or add our thoughts to an existing rail-cap-bass-thread...

[DSP_Geek]

Originally posted by ChocoHolic


...yupp that's exactly why I am wondering when somebody tells me that the supply cap has a major influence on bass control. At these frequencies the PSSR of any normal power amp is 60db or higher (except class D !!!).

The Hypex gang might have something to say about that: according to their spec sheet, PSRR on UcD400s is better than 65 dB on all frequencies.

[jnb]

From the Cornell Dubilier application guide

Self-resonance is typically below 100 kHz depending on
capacitance. At self-resonance the device is resistive and
beyond it is inductive.

Dissipation factor is the measurement of the tangent of the
loss angle (tan ) expressed as a percentage.

ESR declines steadily with increasing frequency and cross-
es over to constant ESR at a frequency inversely propor-
tional to capacitance. This crossover is typically below 10
kHz. The ESR of high-capacitance capacitors changes little
with increasing frequency because high-capacitance causes
them to have low crossover frequencies. The ESRhf ranges
from 0.002 for large, screw-terminal capacitors to 10
for miniature devices.

[Eva]

Originally posted by ChocoHolic


...yupp that's exactly why I am wondering when somebody tells me that the supply cap has a major influence on bass control. At these frequencies the PSSR of any normal power amp is 60db or higher (except class D !!!) .
And in fact I never observed any dominant low frequency artifacts of the rails in my output voltages.
May be we have to dig deeper. If there is a real corelation between supply caps and bass response, then it is not a very obvios one. The obvious straight forward effects are no issue IMHO. At least up to now all my measurements indicate close to perfect behavior in this regard. If all this is not a myth, then there must be a less obvios effect. I know that different bass sound & control is not a myth, even if you only change the amp and keep everything else the some. But I do not know if and how this is really caused by the rail caps.

Hm... may be we should open another thread for this.. or add our thoughts to an existing rail-cap-bass-thread...

I agree, but there is no correlation, this is just another myth. Only bass clipping behaviour depends on how much capacitance is employed.

[gootee]

I found some something that looks GREAT:

http://www.cde.com/applets/CDEspiceApplet/aframe.htm

I am just now getting ready to try this applet. But it looks like EXACTLY what is needed, for modeling frequency-dependent electrolytic capacitor effects in Spice.

And I quote (from the URL above):

"Cornell Dubilier now offers Spice models of many of its wet aluminum electrolytic capacitors. We have a new online impedance modeling applet that allows the user to select any standard catalog part number among 16 types. The capacitance, ESR, and impedance are then graphed versus frequency at several temperatures. A Spice simulation program listing is available with a mere click of a button, and this model is readily cut and pasted into a Spice simulator. This is a new offering from Cornell Dubilier, and we will be refining the models and adding new types over the coming months."

Hallelujah!

- Tom Gootee

http://www.fullnet.com/~tomg/index.html

[gootee]

Attached is a screen-shot of the Cornell Dubilier Impedance Modeler applet. (I had to use Alt-PrtSc to get it to copy the screen to the clipboard, in Internet Explorer.)

I had rested my mouse point on the -40degC curve, at 10 kHz, in the top plot, which brought up the capacitance value under those conditions, seen in the little pop-up box on the plot.

[gootee]

And here is the SPICE model that it generated, for the example capacitor I had selected (12000uF, 25v, 401C series):

CDE Spice Applet for Electrolytic Capacitors, Rev 07-28-03


* INPUTS:
* Part Number: 401C123U025AK8
* Type: 401C
* 3-pin Plug-in Capacitors
* Widest Temperature Range, -55 to +105 ºC
* Diameter: 1.375
* Length: 1.625
* Typical ESR (120 Hz, 25 ºC): 28.7
* 65 ºC DC Capacitance: 10982.4 uF
* Series Inductance: 22.5 nH
* 65 ºC Metal Resistance: 0.0024 ohms
* 65 ºC Spacer-Elyte Resistance: 0.0191 ohms
* 65 ºC Tunnel Resistance: 0.0028 ohms
* 65 ºC Spacer Resistance: 0.0163 ohms
**************************** CORNELL DUBILIER WET ALUMINUM ELECTROLYTIC CAPACITOR SPICE MODEL:
.SUBCKT CDE_WetAluminumElectrolyticCapacitorMIL 1 10 PARAMS: Cnom=10982.4u Ls=22.5n Rm=0.0024 Rspp=0.0163 Rtun=0.0028
* VALID FOR AC, DC, TRANSIENT SPICE ANALYSIS
* MIL ELECTROLYTE PARAMETERS
* BE SURE TO SET TNOM=65 ºC
* VALID FOR RANGE 45-85 ºC ONLY (GENERALLY THIS IS THE RANGE IN WHICH ALUMINUM ELECTROLYTIC CAPACITORS ARE USED)
* SKIN EFFECT IS NOT MODELED
* DIELECTRIC LOSS IS NOT MODELED (BUT DOES NOT AFFECT EXTERNAL CICUIT, ONLY CALCULATED CAPACITOR LOSSES)
* ZENER CLAMPING EFFECT IS NOT MODELED (BUT ONLY AFFECTS EXTERNAL CIRCUIT IF VOLTAGE RATING IS EXCEEDED)
* REVERSE VOLTAGE CLAMPING EFFECT IS NOT MODELED (BUT ONLY AFFECTS EXTERNAL CIRCUIT IF REVERSE VOLTAGE IS APPLIED)
* DC LEAKAGE CURRENT IS NOT MODELED (BUT GENERALLY DOES NOT AFFECT EXTERNAL CIRCUIT IF APPLIED VOLTAGE IS BELOW RATED VOLTAGE)
Lseries 1 2 {Ls}
Rmetal 2 3 {Rm} TC1=0.0039
Rsp 3 4 RT {Rspp}
R1 4 5 RT {0.658*Rtun}
R2 5 6 RT {0.1*Rtun}
R3 6 7 RT {0.05*Rtun}
R4 7 8 RT {0.2*Rtun}
R5 8 9 RT {0.3*Rtun}
C1 5 10 CT {Cnom/32}
C2 6 10 CT {Cnom/16}
C3 7 10 CT {Cnom/8}
C4 8 10 CT {Cnom/4}
C5 9 10 CT {Cnom*0.532}
.MODEL RT RES TC1=-0.00404618508 TC2=0.0000295452624
.MODEL CT CAP TC1=0.001
.ENDS
***************************

[gootee]

The attachment shows the schematic for the capacitor model, that I drew, in LT-Spice, using the CDE model's netlist, from my last post.

[Conrad Hoffman]

Cool, but I'm confused. They say they're not modeling dielectric loss, but that appears to be exactly what they're doing with the frequency dependent resistor. Or are they trying to differentiate between loss mechanisms?

[gootee]

Conrad,

My impression was that they meant that they were not _explicitly_ modeling the dielectric loss, but that it was still lumped-in.

- Tom