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Old 14th September 2006, 03:05 PM   #21
gl is offline gl  United States
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Hi Cheff,

I have a couple of questions about your V3 circuit:

1) Why did you use a 1K load resistor on the output instead of a higher value? With 7ma of bias on the output transistors and a +-17V swing it seems like the transistors would be a bit starved for current at full swing. What did your simulation say? Did you use the low resistor value to reduce the absolute DC offset? With your load in parallel with the 1K resistor the total load will be even worse. Did you simulate the total load?

2) What did you find was the range of adjustment (in mv) with each of the two pots?

Thank you.

Graeme
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Old 14th September 2006, 03:56 PM   #22
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Quote:
Originally posted by gl
Hi Cheff,

I have a couple of questions about your V3 circuit:

1) Why did you use a 1K load resistor on the output instead of a higher value? With 7ma of bias on the output transistors and a +-17V swing it seems like the transistors would be a bit starved for current at full swing. What did your simulation say? Did you use the low resistor value to reduce the absolute DC offset? With your load in parallel with the 1K resistor the total load will be even worse. Did you simulate the total load?

2) What did you find was the range of adjustment (in mv) with each of the two pots?

Thank you.

Graeme
Hi Graeme

OK, that's a real couple Your last couple was a couple of couple

Well, I had to make a compromise here again, since the output
impedance depends on this value (roughly Rout/2). A higher value
leads to a higher Zout, which I found to be undesirable for a preamp.
But Rout also affects the open loop gain, which increases as Rout
increases.

With a 10K pot at output, it doesn't affect Zout that much, so total
load won't have a great influence.

Rout also helps stabilizing the output offset, providing a reference
to ground to the collectors junction when the outputs are unloaded
(no pot), and a higher value would have increase the offset
instability as it amplifies any difference between the collectors
currents (Rout x Idiff)

So it's all about compromises, but my main concern was to keep a
relatively low Zout. And luckily, this value seems to have more
advantages than drawbacks

For the offset range, I haven't paid much attention to the limit
values, but my bad memory seems to say something like +/-20mV
for both... But I may be wrong here, so I'll try to check...

Oh my god... I'll have to detune this fabulous offset I've been
hunting for so long ...

Regards
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Old 15th September 2006, 06:51 AM   #23
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Default Progress

Hello Cheff - thank you for your reply.

It was, in fact, your suggestion to consider transistors, other than the Zetex, that saved me. My ICAPs models for the Zetex must have been corrupt or highly incorrect (inappropriately applied?). When I replaced the models with Linear BC550/560 part models, which I downloaded from their website, the circuit suddenly sprung to life and simulations now make sense. I have just a couple questions for you:

1) Do you have any suggestions for designing for a SE input to SE out? I believe reducing the Rout to 500-ohms will help in that case, but the output swing is reduced by 1/2 (1/4 of balanced swing). Also, I simulate a slight differential offset when the negative input is grounded for SE operation. Any ideas how to add options to improve the output swing and/or diff offset in SE operation?

2) Iím curious why you chose to use the level-shifter current-mirror for output stage and not a FET, like in many other designs. Isnít the linearity of the FET better when well biased? Did you get a chance to test the different emitter resistor values?

3) I simulated a 0.063% THD at 1K. Seems a bit high. Is that about youíre your sims showed? I know you measured quite a bit lower with the soundcard.

4) What are you using for PS? Why no local capacitors on the preamp boards? How about a LP filter on the input supplies?

5) Would gate-stoppers be prudent on the JFETs (~100-ohms)? Iím not sure theyíre needed for RF on JFETs, but Iíve seen them used.

6) What are you using for volume control at the output? Did you say 10K pot? I was thinking a vol ladder, something like the twisted-pair JT.

7) Do you have a .pdf layout available for the V3 design yet?

Sorry for the seven xís seven questions. Anything you can provide will help.

Thanks, Willus
Attached Files
File Type: pdf ugs_pre_1_sim_2.pdf (79.1 KB, 770 views)
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Old 15th September 2006, 01:35 PM   #24
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Default Re: Progress

Quote:
Originally posted by z_willus_d
Hello Cheff - thank you for your reply.

It was, in fact, your suggestion to consider transistors, other than the Zetex, that saved me. My ICAPs models for the Zetex must have been corrupt or highly incorrect (inappropriately applied?). When I replaced the models with Linear BC550/560 part models, which I downloaded from their website, the circuit suddenly sprung to life and simulations now make sense.
Glad you have it working

Quote:
I have just a couple questions for you:
The couple's now seven Everyday's inflation

Quote:
1) Do you have any suggestions for designing for a SE input to SE out? I believe reducing the Rout to 500-ohms will help in that case, but the output swing is reduced by 1/2 (1/4 of balanced swing). Also, I simulate a slight differential offset when the negative input is grounded for SE operation. Any ideas how to add options to improve the output swing and/or diff offset in SE operation?
I don't understand what you mean by SE in/out. Do you mean
Balanced/Unbalanced (sorry, english is not my native language...
Nobody's perfect) And why would you like to reduce Rout ?
The offset you simulate in unbalanced mode, is it a static or
dynamic one ?

I got no static offset when grounding one input in my sims.
And if I plot (V(out+)+V(out-)) in transient analysis (one input
grouded), I get for example a 25mV pp signal with a 6.5V pp.
Is it what you call an offset ?

Quote:
2) Iím curious why you chose to use the level-shifter current-mirror for output stage and not a FET, like in many other designs. Isnít the linearity of the FET better when well biased? Did you get a chance to test the different emitter resistor values?
I have chosen the current mirrors on an audio basis. For me, it was
far better than mosfets. Mosfet biasing was thermally limited by the
E-line package dissipation capabilities, but mostly by the offset
unstability when the mosfets were too hot. But you're welcome to try
And I will test different emitter resistor values, but give me one
week or two to listen to music

Quote:
3) I simulated a 0.063% THD at 1K. Seems a bit high. Is that about youíre your sims showed? I know you measured quite a bit lower with the soundcard.
Mine gives 0.008% @ 1K, but I do not trust my simulator. Nor my
soundcard But it gives an idea...

Quote:
4) What are you using for PS? Why no local capacitors on the preamp boards? How about a LP filter on the input supplies?
The PS is inspired from the Pearl's supply (see attached file)
There's no local caps, but the supply's output caps are close to the module :

Click the image to open in full size.

The supply's on the right of the module (old ones ). And I didn't
feel the need for additional caps, nor of an additionnal ps filter.

Quote:
5) Would gate-stoppers be prudent on the JFETs (~100-ohms)? Iím not sure theyíre needed for RF on JFETs, but Iíve seen them used.
Well, I didn't have problems with oscillations due to the lack of gate
resistors. But I have very short tracks on the pcb, so it may help.
But feel free to use some if you think it's more prudent. Or add a
ferrite bead on each gate lead before soldering the fets.

Quote:
6) What are you using for volume control at the output? Did you say 10K pot? I was thinking a vol ladder, something like the twisted-pair JT.
I use a balanced relay-based volume control (see the photo above -
it is hidden by the supply and the module), with a constant input
impedance of 10K :

Click the image to open in full size.

Errr, what's a JT ?

Quote:
7) Do you have a .pdf layout available for the V3 design yet?
See next post

Quote:
Sorry for the seven xís seven questions. Anything you can provide will help.
You're welcome
Attached Images
File Type: gif ugsalim1.gif (20.5 KB, 8969 views)
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Old 15th September 2006, 01:37 PM   #25
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So here is the pdf file for the pcb.

UGS V3 PCB

Sorry, but it's double-sided Take care of the scale when printing it, the actual module dimensions are given on page 2, along with the stuffing guide.

These are mirrored pcbs, so be careful before going U.V.

I added room for some compensation caps (CFB) if you happen to see some overshoot on square signals. Just in case, as I didn't find them necessary on my version...

Enjoy.
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Old 15th September 2006, 04:19 PM   #26
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Merci, Cheff.
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Old 15th September 2006, 04:30 PM   #27
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CheffDeGaar,

UGS V3 PCB

Wouahhhh, such a great job, will save me hours of design,

Thanks so much!!!

Alain.
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Old 15th September 2006, 05:57 PM   #28
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Cheff,

Congratulation on your very well implemented circuit. You make me want to upgrade from my X-BoSoZ. That last photo is a doozy, you spent a great deal of effort on integrating your circuitry together, and I'm impressed and jealous! Care to post a few more?!?

Cheers,
Terry
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Old 15th September 2006, 06:19 PM   #29
jleaman is offline jleaman  Belgium
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Quote:
Originally posted by metalman
Cheff,

Congratulation on your very well implemented circuit. You make me want to upgrade from my X-BoSoZ. That last photo is a doozy, you spent a great deal of effort on integrating your circuitry together, and I'm impressed and jealous! Care to post a few more?!?

Cheers,
Terry
I agree maybe we can get a few made. ID like one.. Looks nice totally. Clean and straight forwared AND well layed out in order.
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Old 15th September 2006, 08:58 PM   #30
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Thanks gentlemen

So some photos of my last toy (old ugs modules inside at the time of photographs)

Click the image to open in full size.

Click the image to open in full size.

Click the image to open in full size.

And how it glows in the dark :

Click the image to open in full size.

But do not forget the important things here are the little heatsinked stamps

Regards,
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