Y.A.F5Tv3.B.T. Yet another F5Tv3 Build Thread

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In the calculation, i have to account the dissipation of the 8 mur3020 ?
from my point of view, they have a very low resistance, so the heat dissipated is quite low... but maybe i am wrong.
From before i have estimate a total power dissipation from the mosfets, but how i need to weight the diodes ? (from a thermal perspective)

Every channel has 8 mosfets and 8 diodes, in the attached simulation i have calculated with a total power dissipation of 140w (and an ambient temp of 30degC).
I think i can push a little bit more on this chunk of aluminium.
 

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in moments of peak currents , current is practically subtracted from mosfets , and given to speaker

so , sum dissipation on heatsink is declining ,so you can ignore dissipation on/through diodes

if you're going full bang , counting on heavy AB class work of F5T , then you really need to carefully calculate everything .....
 
The jfets aren't that sensitive to Vds.
Your choice.
I would be happy at anything between 13V and 20V on the jfets.

Usually a good rule of thumb is maximum peak input signal + 10V. Assuming 2.8V peak input then 13V is quite good.
the input jFET is a voltage to current conversion stage.
You input a voltage and the jFET output is a current.

The input jFET can operate with a Vds of 2 volts even though the input voltage can swing to over 2Vpk.
If you add on a cascode you can run with a Vds anywhere from ~2Vds to the maximum where base current leakage starts to become unmanagable.

The drain resistor converts the output current back into a voltage read by the next stage.

This drain resistor having a voltage output is what needs voltage to allow that swing.
The drain resistor is above the cascode.
The jFET does NOT need an extra 10V above the input signal.
The purpose of the cascode is to separate the jFET from the effects of the high supply rail voltage.
 
the input jFET is a voltage to current conversion stage.
You input a voltage and the jFET output is a current.

The input jFET can operate with a Vds of 2 volts even though the input voltage can swing to over 2Vpk.
If you add on a cascode you can run with a Vds anywhere from ~2Vds to the maximum where base current leakage starts to become unmanagable.

The drain resistor converts the output current back into a voltage read by the next stage.

This drain resistor having a voltage output is what needs voltage to allow that swing.
The drain resistor is above the cascode.
The jFET does NOT need an extra 10V above the input signal.
The purpose of the cascode is to separate the jFET from the effects of the high supply rail voltage.

said that, there is a particular sweet spot for the sk170/sj74 ?
i also imagine that if the cascode device needs to regulate more and more the voltage down then its dissipation figure start to increase. not so much because the current involved are very little...
 
said that, there is a particular sweet spot for the sk170/sj74 ?
i also imagine that if the cascode device needs to regulate more and more the voltage down then its dissipation figure start to increase. not so much because the current involved are very little...

Don't get confused, just copy Nelson if you don't understand.
I notice that it is usually between 12V and 14V when cascoding.
 
Nelson seems to use @ 10v on the v3 schematic with 32v rail so i will go with them.

In your opinion, there's a practical way to guestimate the power dissipation that comes from each of 8 diodes (mur3020). I want to optimize a little bit the placement of the whole board assembly on the heatsink and i am thinking to shift a little bit the board to get the most "hot" components (mosfets) in the center.
 
I was looking into power supply options...
i will start with relatively low bias setting, but i plan to rise as much as possible to extend the class-A region.

Obviously the ripple will rise with it and for limiting the input bulk-capacitance i am start thinking about something like the zenV4 capacitance multiplier / regulator.

I made a sim in spice and it seems to works quite OK. i see that i will loose some voltage and the dissipation is around 25w for 6amp bias (too much... i know).

For sure i need to swap the irfp240 with something more beefier because the power dissipation at startup exceed specs.

What do you think about ?
 

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you should have 15V or more to the J-fets. and the outputs should be mounted 1/3 up from the bottom of the sinks.

i was talking about centering in the horizontal offset rather than vertical.
If i can estimate how much the diodes dissipate on the heatsink i can simulate more accurately where to fix all the assembly in order to maximize heat distribution.
 

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Just pair up the mosfets, or you can buy some hockey pucks.

I have simulated with 2xirfp240 (i will use the ones that doesn't fit in the matching for the outputs) and it works fine.

I have tried also to simulate the transformer with a load of 6A (... go to extreme limits) and i've seen that the secondary voltage will be in the region of 68v to obtain 44v output. Maybe something in my spice model of the transformer is wrong... but for me seems a lot of dropout.

Can someone have a look at the attached sim ?
 

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i was talking about centering in the horizontal offset rather than vertical.
If i can estimate how much the diodes dissipate on the heatsink i can simulate more accurately where to fix all the assembly in order to maximize heat distribution.
The bottom PMOS will run cooler than all the others.
The upper group of NMOS will run hotter than the lower group of PMOS.
Within the lower group the first will be coolest, the second will be warmer, the third will be hotter and the 4th may be about the same temp.

In the upper group, there will be a similar gradation of temperatures from 5th to 8th.

Heatsink manufacturers give spacing advice for groups of devices. See what you can find.
 
The bottom PMOS will run cooler than all the others.
The upper group of NMOS will run hotter than the lower group of PMOS.
Within the lower group the first will be coolest, the second will be warmer, the third will be hotter and the 4th may be about the same temp.

In the upper group, there will be a similar gradation of temperatures from 5th to 8th.

Heatsink manufacturers give spacing advice for groups of devices. See what you can find.

Yes, the simulation confirms that.
but i was talking about centering on the horizontal plane (look at the photo).

i need to know the heat output from diodes so i can keep the mosfet as centered as possible if the diodes dissipate less.

but i want to do this optimization via the simulations, and a rought estimate of the heat output from diodes will help
 
the F5t diodes should not pass for normal/average outputs.
The diodes are there to reduce voltage losses when transients peaks are demanded.
i.e. they turn on ONLY when the current demand is approaching current clipping.
When they do turn on it is for very short duration and should be at a very low duty cycle.
This method of setting up the diodes means they do not generate heat. The heatsink heats them up.
 
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the F5t diodes should not pass for normal/average outputs.
The diodes are there to reduce voltage losses when transients peaks are demanded.
i.e. they turn on ONLY when the current demand is approaching current clipping.
When they do turn on it is for very short duration and should be at a very low duty cycle.
This method of setting up the diodes means they do not generate heat. The heatsink heats them up.

I think i got it, they are used like a dynamic bypass for the de-gen resistors.
The principle of when they conducts or not is still a bit foggy for me... needs more investigation/explanation.

So in the end i will center the active devices in the heatsink for a more even distribution and let the diodes heats. (i think they will need to stay thermally close so there will be less thermal drift... i guess).

Anyone has considerations about the regulator ? is it possible that i need to have 60V input to obtain 45v clean after the reg ?
maybe i need to check with the real transformer...
 
They are arrived.
2x 1400VA
primary 0-230 (saturation @ 290v)
secondary 0-38 (loaded)
secondary 0-38 (loaded)

i am still waiting for a permalloy strip to wrap around, but i have added a screen winding between primary and secondary.

I will begin to design the regulator pcb, i think i will go with irfp240/9240 as active elements, i think there are better choices out there... but i am not aware of.
 

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