Here is a comparison of the Vgs vs. temperature behavior of the IXFN44N80Q3 and IXTN40P50P FETs, at Vds=24V and Ibias=1.5A. Here are the linear fits to the curves:
- IXFN44N80Q3: Vgs= 5.727 -0.00874*Temp
- IXTN40P50P: Vgs= 3.361 -0.00307*Temp
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Thanks to 2picodumbs, who told me how to get the better models working. It was of course as mostly a change in the normal nm and pm .asy necessary. Concerning D S and G and the corresponding netlist order number.
And it seems the new models give less distortion at 1W. Of course I readjusted the cascode feedback resistor. This time I put a 220uF cap in the path, so I do not always have to readjust the offset.
And it seems the new models give less distortion at 1W. Of course I readjusted the cascode feedback resistor. This time I put a 220uF cap in the path, so I do not always have to readjust the offset.
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Yes. The front-end (FE) has a fairly high open-loop gain and is very sensitive to the JFET drain load resistances and thermal drift unless you apply some significant negative feedback (DC coupled) to the FE output. Increase the overall open-loop gain by greatly increasing or eliminating the load resistor on the FE output. This will both stabilize the DC offset on the FE output and reduce the FE output impedance for better drive of the capacitive load of the output FET gates. All you need to do with the circuit in post #363 is:
- remove your AC coupled cascode feedback.
- remove (or increase) the FE ouput load resistor.
- add appropriately sized (DC coupled) resistors to each cascode feedback point. H2/H3 polarity and level control is possible by sizing the resistors unequally.
- adjust the global feedback resistor to achieve the closed-loop gain.
There are other ways to accomplish the same, such as shown here:
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THX
Somerimes after sitting hours with Spice simulations one CFB resistor is very pleasant.
Still the values and number of resistors and way of local feedback are floating....
Some good news. I ran some Vgs vs. temperature measurements of a n undegenerated 2SK2013 at Id=50mA, Vds=24V, mounted on an Aavid Thermalloy 532-551002B00G heatsink rated at 12C/W. It looks like there is little danger of thermal runaway at these power levels with a modest heatsink. Bottom line: no need to prefer Hitachi laterals vs. Toshiba VDMOS FETs because of fear of thermal problems with undegenerated Toshibas.
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Even if ya don't have faith in the dumbness of picodumb, learn to interpret data sheets.The way Lhquam is presenting the fact is more convincing.....
Dumb bastards.
But I still love ya brothers.
I need to be careful here to maintain dumbness credibility.
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Even if ya don't have faith in the dumbness of picodumb, learn to interpret data sheets.
Dumb bastards.
But I still love ya brothers.
I need to be careful here to maintain dumbness credibility.
Still Love? Ever!
Indeed the problem is that I cannot interprete the data sheets in this point concerning thermal behaviour . Completely right!
Here is a Gm vs. I(d) plot for the 2sk2013. It tracks excellently with the datasheet.
BUT, the bias situation is far from perfect.
At 50mA, Gm=.3 S. The Vgs vs. temperature plot in post #373 has a slope of -1.8mV/C. If the bias current is adjusted for 50mA at an operating temperature 20C above ambient, the bias current will be 1.8mV/C * 20C * .3 S = 10. 8mA lower at the ambient startuptemperature.
BUT, the bias situation is far from perfect.
At 50mA, Gm=.3 S. The Vgs vs. temperature plot in post #373 has a slope of -1.8mV/C. If the bias current is adjusted for 50mA at an operating temperature 20C above ambient, the bias current will be 1.8mV/C * 20C * .3 S = 10. 8mA lower at the ambient startuptemperature.
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