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Old 14th August 2012, 06:00 PM   #771
lhquam is offline lhquam  United States
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Quote:
Originally Posted by Zen Mod View Post
what you mean with parasitic currents ?

loading of secondary is of most importance here
Referring back to post 742 F6 Amplifier, is there any problem using method B if an appropriate load resistor is placed across the secondary? As discussed earlier, method B might suffer more from xformer parasitic currents, but has fewer capacitors involved.
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Old 14th August 2012, 06:34 PM   #772
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looking at pic from #742 (attached )

in case B AC path for modulation is through C4 , which serve also as bias voltage blocking/maintaining/smoothing cap

in case A AC path for modulation is through C1 ; in that case C3 is just bias voltage blocking/maintaining/smoothing cap

Click the image to open in full size.
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Old 14th August 2012, 08:11 PM   #773
lhquam is offline lhquam  United States
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Originally Posted by Zen Mod View Post
looking at pic from #742 (attached )

in case B AC path for modulation is through C4 , which serve also as bias voltage blocking/maintaining/smoothing cap

in case A AC path for modulation is through C1 ; in that case C3 is just bias voltage blocking/maintaining/smoothing cap
Can C4 serve both duties as well as C1/C3 in method A?
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Old 14th August 2012, 08:39 PM   #774
lhquam is offline lhquam  United States
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Default Secondary loading alternatives

In the following drawing, methods B1, A1, and A2 show some alternatives for loading secondary winding and biasing the output FET. In all cases, Rsec is the secondary load resistance.
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File Type: jpg Bias-methods2.jpg (54.3 KB, 350 views)
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Old 14th August 2012, 09:02 PM   #775
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Originally Posted by lhquam View Post
Can C4 serve both duties as well as C1/C3 in method A?

it is not an issue

fact is that in both cases we are having one cap in series with secondary

and in case A it's possible to have adequate loading of secondary
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Old 14th August 2012, 09:06 PM   #776
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Originally Posted by lhquam View Post
In the following drawing, methods B1, A1, and A2 show some alternatives for loading secondary winding and biasing the output FET. In all cases, Rsec is the secondary load resistance.
if you ask me - any of A derivatives

which one suits you most ......
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Old 14th August 2012, 10:38 PM   #777
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Originally Posted by Zen Mod View Post
if you ask me - any of A derivatives

which one suits you most ......
I don't like caps in the signal path. They make me want to buy $100 each or more caps and worry why I was too cheap to buy Audionote $1000 silver foil caps. So my 1st preference is "B".
Then it occurred to me that sometimes we do things that make the output device exhale the smoke within. Does this trick of letting the smoke out ever short the gate to a rail and possibly burn out a winding on the secondary?
That would be bad, making me reconsider "A". But I don't know the likely hood of that. I have not let the smoke out yet.

Rush
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Old 14th August 2012, 10:47 PM   #778
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I told ya - in B you have cap in AC path , too

think about impedances
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Old 14th August 2012, 10:58 PM   #779
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Quote:
Originally Posted by Zen Mod View Post
I told ya - in B you have cap in AC path , too

think about impedances
Yes, but, the cap is on the non-signal side of the winding where the AC goes to ground (or rail) with a lot of impedance between, so I think the cap is less critical than halving the full signal coupling through a cap.

I could be wrong, but that is what I think right now,

Rush
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Old 14th August 2012, 11:41 PM   #780
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there is no non-signal side

even in case of B1 case (post #774) , where you have proper loading resistor across secondary , value of C2 must be sized accordingly to wiper-lower end section of trimpot , calculated as bypass cap , or it will not serve prescribed duty

in that case - it's AC impedance is low , so trimpot value is of no importance , AC wise

conclusion - cap is in AC signal path ...... as it must be , because Jfet likes to see signal between S and G

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