Making assumptions is always a problem with audio, where the "standards" have always been loose.
Most preamps will put out 4V RMS or more into a 10K load.
Some of the tube preamps will put out 25V RMS, IIRC.
Doug
voltage gain is +26dB +-0.5dB, i.e. 20times.
BTW,
+-0.5dB is atrocious in this context. If they can't control gain to better than +-0.1dB they should not be manufacturing amplifiers and asking us to pay for them.
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Thanks a lot guys; I learned a lot here in a few posts; gives me a whole new perspective; must do more homework.
The B1 works fine here with 2 9 Volts rechargable batteries; and I enjoy my UC180 as well in spite of the last figures Andrew mentions, which don't mean much to me, as a nitwit.
I also use a 20 year old Benytone X-Calibre pre amp, which has had a revision and is very good. Nobody has heard of it. Some try-out byline of Luxman they say.
That's for when I want to be blown out of the room, which is not very often.
Ruudjoo
The B1 works fine here with 2 9 Volts rechargable batteries; and I enjoy my UC180 as well in spite of the last figures Andrew mentions, which don't mean much to me, as a nitwit.
I also use a 20 year old Benytone X-Calibre pre amp, which has had a revision and is very good. Nobody has heard of it. Some try-out byline of Luxman they say.
That's for when I want to be blown out of the room, which is not very often.
Ruudjoo
Read this thread from beginning to end tonight. Really ejoyed getting acquainted with Babowana! Wishing you the best of health, young man!
Also really impressed with helpfulness of DIY'ers.
Looking forward to building a B1 as my first diy project in the last 40 years, with the help of a friend who is an audio electronics tech. Cheers eveyone.
Also really impressed with helpfulness of DIY'ers.
Looking forward to building a B1 as my first diy project in the last 40 years, with the help of a friend who is an audio electronics tech. Cheers eveyone.
OK, I got me some 2SK170BL's today and have these Idss values.
About the higher and lower Idss in a pair, which goes where? The higher Idss for Q100 the lower for Q101?
Thanks!
- 7.96
- 6.37
- 7.39
- 8.56
- 7.11
- 6.79
- 8.07
- 8.32
- 8.48
- 8.44
- 8.46
- 8.13
- 7.39
- 8.41
- 7.93
- 6.57
- 7.63
- 7.93
- 7.3
- 8.47
- 7.00
- 7.90
- 7.87
- 8.12
- 7.46
- 8.35
- 8.45
- 8.35
- 7.69
- 7.09
About the higher and lower Idss in a pair, which goes where? The higher Idss for Q100 the lower for Q101?
Thanks!
This is such a great question. It has been asked and answered in the B-1 Buffer thread. The device symbol for an asymmetrical JFET is misleading. The gate "arrow" should not be pointing straight across from the source connection to the channel. What happens when the FET leaves triode to enter pentode territory? The device symbol should have the gate arrow located 2/3 the way down the channel toward the source to indicate asymmetry and, at the same time, to indicate an internal channel resistance between the gate and the source. Idss, if I have a grasp on this, becomes "stable" at DS voltages that exceed the absolute value of the pinch off voltage. Self-biasing requires a voltage drop across an internal source resistor, local feedback, and the mechanisms of a depletion region.
Which device, if not balanced, do you want held at Idss? I don't know. Nevertheless, there seems to be agreement that the signal device (Q100) should be in saturation. Thus, the higher Idss device is perhaps better placed as Q101 so to hold Q100 at Idss. It would be interesting if you measured Vp (pinch off) for the devices you are about to match on the basis of Idss. If you could match -.63 for Vp and at the same time, match Idss,..... thermal distortion. Regardless, I doubt that it matters which device you put in the Q101 position as long as the drain of Q101 is somewhere near 1/2 the PS voltage and that maximum signal transients are not clipped. In the case of blueprinting the circuit I suspect that there is a rationale for deciding the placement of Q100/101; perhaps aimed at linearity.
I have, in fact, wondered if there was merit to intentionally mismatching Q100 and Q101 so that Q101 could be stabilized with a source resistor while Q100 was held in saturation. Or, what is the downside of stabilizing the circuit with source resistors on each FET of a perfectly matched Q100/101? Noise, I imagine. The B-1 circuit is wonderfully "simple" and elegant.
Which device, if not balanced, do you want held at Idss? I don't know. Nevertheless, there seems to be agreement that the signal device (Q100) should be in saturation. Thus, the higher Idss device is perhaps better placed as Q101 so to hold Q100 at Idss. It would be interesting if you measured Vp (pinch off) for the devices you are about to match on the basis of Idss. If you could match -.63 for Vp and at the same time, match Idss,..... thermal distortion. Regardless, I doubt that it matters which device you put in the Q101 position as long as the drain of Q101 is somewhere near 1/2 the PS voltage and that maximum signal transients are not clipped. In the case of blueprinting the circuit I suspect that there is a rationale for deciding the placement of Q100/101; perhaps aimed at linearity.
I have, in fact, wondered if there was merit to intentionally mismatching Q100 and Q101 so that Q101 could be stabilized with a source resistor while Q100 was held in saturation. Or, what is the downside of stabilizing the circuit with source resistors on each FET of a perfectly matched Q100/101? Noise, I imagine. The B-1 circuit is wonderfully "simple" and elegant.
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