JFET Basics

[RCruz]

I am opening this new thread hoping to get some better insight regarding jfet implementations.

From reading Horowitz & Hill, I understand that for a given Vds, if we set
Vgs = 0, Ids is fixed at Idss.

If Vgs is reduced, Ids is also reduced until it stops (pinchof)

In this book, I found a picture with jfet characteristic curves where I can see Id = Idss for Vgs=0 but if Vgs >0 than Id is higher than Idss.

I also read elsewhere that one should never allow a positive Vgs because that could let the current flow from Drain to Gate with disastrous results.


So my first question is:

Can a jfet operate at Id higher than Idss ?

[juma]

http://www.tkhifi.com/div/Erno_Borbe..._articel_1.pdf

http://www.tkhifi.com/div/Erno_Borbe..._articel_2.pdf

[Cobra2]

The Borbely articles are good, but they are written by a man that have lived with FETs for a lifetime, not easy to grasp all for a beginner...

Arne K

[buzzforb]

Originally Posted by RCruz

Can a jfet operate at Id higher than Idss ?

No. Read Borberly articles as Juma suggested. Also there is AN102 and AN103. Google it.

[Zen Mod]

yes - it can ;

but - not for long

[juma]

Operating a JFET at Id > Idss is not a problem per se, as long as you keep the Pd under dangerous level. The problem is that at Id > Idss significant current starts to flow through the gate. That way you lose the important property of JFET - the high input impedance and you are out of linear working regime.
That's not a big problem in switching mode but that's not what we here usually use the JFETS for.

[RCruz]

Thank you ... now I understand I must never let Vgs become positive otherwise I will have leaking gate current.

I will reread EB articles now

[scott wurcer]

Marshal Leach's class notes are a good resource.

http://users.ece.gatech.edu/mleach/e...et/thejfet.pdf

[RCruz]

Thank you Scott

Food for the mind

[merlin el mago]

Ricardo you can ask directly to Erno Borbely in his Facebook.