Sorry guys, beginner question alert: I came across this paper which describes measuring the input capacitance "using a known capacitance in series with the input of the amplifier and measuring the change in apparent amplifier gain as a function of capacitance."
Is this one of the three methods already talked about?
http://tf.nist.gov/general/pdf/821.pdf
Is this one of the three methods already talked about?
http://tf.nist.gov/general/pdf/821.pdf
Didn't Bob Pease propose a 2N4117 connected like this, when you wanted a low cost pA diode?
Gerhard
I asked for the procedures used by Toshiba, NXP, and Fairchild.
They may or may not be the same. There is nothing magical about the number three.
Toshiba and NXP don't seem to publish the method they have used.
Fairchild even usually don't publish more device data that fits on
the cover page of the data sheet :-(
Connelly&Motchenbacher comment on amplifier input impedance measurement
that this can be confusing, especially in the case of inverting amps
where gain is -Rf/Rg.
Inserting a resistor messes up the gain.
They say that for small source impedance, the bridge is correct and
for large source impedance inserting a resistor/cap.
Gerhard
And the Lord spake, saying, "First shalt thou take out the Holy Pin, then shalt thou count to three, no more, no less.
Three shall be the number thou shalt count, and the number of the counting shall be three.
Four shalt thou not count, neither count thou two, excepting that thou then proceedest on to three. Five is right out.
Once the number three, being the third number, be reached, then lobbest thou thy Holy Hand Grenade of Antioch towards thy foe,
who being naughty in my sight, shall snuff it." Amen.
http://www.youtube.com/watch?v=3ioXrZT9Ric
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Yes, typically sub 100fA. This whole thing about FET symmetry is interesting, as I recall swapping drain and source on a 2SK170 gave me the same Vp and Idss so the gate to drain and gate to source junctions would seem the same.
The same is probably true for those lateral PNP bipolars. Equally bad wether reversed or not.
Making a transistor asymmetric is an optimization, i.e. extra fat doping for the collector
well to get low resistance above the substrate etc. I'm sure you know more about that
than me...
I have swapped drain & source for BF862s last week in a low noise oscillator circuit for
mechanical reasons because it was easier to solder on a board that develops from
shiny gold plated back to dead bug style....
I really was convinced that I was through with it. :-(
BF510 however is asymmetric. So says the first word under DESCRIPTION.
<NXP Semiconductors[pip=BF510_511_512_513_CNV_2]|pp=[t=pip,i=BF510_511_512_513_CNV_2]>
(the url is * up when i paste it into this editor... but still easy to find)
regards, Gerhard
There is only one junction in the JFET. It is between the gate and the channel.
Source and drain are only the ends of the channel. Since there is a voltage drop
across the channel, the depletion zone at the drain is wider than at the source.
This results in less capacitance between gate and drain because the capacitor
plates are further apart.
In Massobrio/Antognettit "Semiconductor Device Modeling with SPICE"
is a nice picture of this on the second page of the JFET chapter, and it is probably
in every beginner textbook.
Search for pinch-off point of the channel etc.
So, if you reverse the FET, the pinch-off point will be mechanically on the
other side, too.
Gerhard
OK, graphically there is a second junction on the substrate side, but this is
exactly in parallel to the top one. The reason why in metal case JFETs the
gate is usually on the case.
Have not had the chance, my gear is in a state of flux right now. From the text book model there is symmetry as mentioned above, if the channel is doped uniformly there is only one type junction. For RF FETs sometimes there are parasitics that make small differences.
On second thought this is making a mountain out of a mole hill, a small error in reading the data could give a large error in curve fitting and maybe the difference is trivial and not that large. In any case the models on the web are all over the place. Back to regular programming
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Sorry John for only engaging 1/2 my brain. Of course both the LSK170 and 2SK170 look symmetric and they measure roughly that way. They both (at least my samples of one) look to be a little better than the DS. The LSK part looks much better than that model they provide.
It only takes a small slip of the ruler to misread one of those tiny log log plots.
It only takes a small slip of the ruler to misread one of those tiny log log plots.
Suggest Simon7000 that you open a new thread, in an appropriate sub section of this forum on this topic??
Would be very interested in what you find, and your test methodology.
Probably would be a good idea to test different brands rather than a run of a single brand many examples.
Be sure to try a Caddock or Vishay (bulk film type) as a "gold standard".
_-_-bear
Would be very interested in what you find, and your test methodology.
Probably would be a good idea to test different brands rather than a run of a single brand many examples.
Be sure to try a Caddock or Vishay (bulk film type) as a "gold standard".
_-_-bear
I am acquiring every kind I can get. All 1K preferably 1/4W because at the levels I can source they will have a bit more thermal problems than 1/2W.
Anybody have 2 old 1K 1/2 Resistas?
A thread is not appropriate as most I am not really interested in idle chatter. Publishing is more appropriate.
Simon7000,
Are you testing the thermal stressing of resistors WRT signal?
If so, can we not merely design with higher wattage resistors and avoid the problem entirely by not designing "on the edge"??
Is this question "idle chatter"?
dunno... (rhetorical?)
I guess if John Curl is ok with this topic here, I am... but it seems like it is OT to some extent.
I'll be looking for your published paper in JAES or another journal? C'mon... just joking here.
_-_-bear
Are you testing the thermal stressing of resistors WRT signal?
If so, can we not merely design with higher wattage resistors and avoid the problem entirely by not designing "on the edge"??
Is this question "idle chatter"?
dunno... (rhetorical?)
I guess if John Curl is ok with this topic here, I am... but it seems like it is OT to some extent.
I'll be looking for your published paper in JAES or another journal? C'mon... just joking here.
_-_-bear
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