Hi qusp, you look like a detective
Yes, the part is Si5338.
I agree with you that there are some marketing terms.
haha no, my 'google fu' mustve just been good that night. I didnt get any hits on your board specifically, it just seemed the most likely part after a quick glance at the datasheet. I typed in 'T-clock zero ppm' and there was only part from Ti, which has 50ppm jitter mentioned in the google hit, then an on-semi part, which I just glossed over. I completely guessed the Si based on having the best printed headline datasheet jitter numbers, but they looked to me like an illusion, especially for audio. I didnt read any other datasheet.
Status
Hi All,
The boards are in fab now and expected sometime next week. Thank you to all those who signed up. There are still a few more available, after which this GB and offer will be closed.
As you can see from the board layout I have opted for Potsemi output stages. These will give better performance especially output drive to DAC inputs. In most cases DAC may be located away from this re-clocker module and connection will be with lengths of cable. Usually this type of signal distribution suits a more elaborate differential drive technique (like ECL or LVDS) but if Potsemi's claim is anything to go by we could get similar benefits from their cmos technology- as described here
Hi All,
The boards are in fab now and expected sometime next week. Thank you to all those who signed up. There are still a few more available, after which this GB and offer will be closed.
As you can see from the board layout I have opted for Potsemi output stages. These will give better performance especially output drive to DAC inputs. In most cases DAC may be located away from this re-clocker module and connection will be with lengths of cable. Usually this type of signal distribution suits a more elaborate differential drive technique (like ECL or LVDS) but if Potsemi's claim is anything to go by we could get similar benefits from their cmos technology- as described here
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Hey Guys. Finally got around to dropping in a 302 with a couple of oscillators programmed at 90.x & 98.x. I'm using an Isolator with a 712 dropped in, with an Amanero flashed for slave 22/24. Anyway, PCM works fine, but the 9018 isn't switching to DSD mode. Since the flash is now using the DSD ON pin for external MCLK, I'm not sure how it can :-| What am I missing?
I hope I'm in for a full sync board. That's $10/shipped for S01/S02 purchasers, right?
I have an S01 board built up with no MCK out parts. I'm doing P-Sync with the on-board clock from a Curryman ES9023 board. I built everything else save casing and wiring the dang thing up. Can't wait for the defining moment. I'm waiting until I can get my casing situation worked out. I don't have the proper tools to do a really nice job nor the space to do it. Live in an apt. Anyways... I'm really pumped about these boards and what they might do for my projects.
I have an S01 board built up with no MCK out parts. I'm doing P-Sync with the on-board clock from a Curryman ES9023 board. I built everything else save casing and wiring the dang thing up. Can't wait for the defining moment. I'm waiting until I can get my casing situation worked out. I don't have the proper tools to do a really nice job nor the space to do it. Live in an apt. Anyways... I'm really pumped about these boards and what they might do for my projects.
There is a mistake in the App Notes.pdf, pin 7 is unaffected by slave mode and remains DSD_OE after flashing. It is only pin 6 that changes from output to input when slave mode firm is flashed.
I asked him some time ago and this was his answer:
-Sorry but i was a bit tired due to the travel. It's not Pin 7 but Pin 6.
The MCLK actually in output becomes an Input.
Thank you Jackal29a!
This has obviously messed up the design
I will see if there is a workaround
BTW is there a 45/49MHz mode?
Full Sync mode with Amanero firmware update
For Full Sync mode with Amanero firmware update:
Looks like we have to cut the track of the ALK-AMN boards to pin#7 (DSDOE) and then connect pin#3 of U8(or U2) with IL712 to pin#7 (MCK) of Amanero. This affects the S01, S02 and the new S03 boards used this way.
Thank you Jackal29a!
This has obviously messed up the design
I will see if there is a workaround
BTW is there a 45/49MHz mode?
For Full Sync mode with Amanero firmware update:
Looks like we have to cut the track of the ALK-AMN boards to pin#7 (DSDOE) and then connect pin#3 of U8(or U2) with IL712 to pin#7 (MCK) of Amanero. This affects the S01, S02 and the new S03 boards used this way.
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Thank you Jackal29a!
This has obviously messed up the design
I will see if there is a workaround
BTW is there a 45/49MHz mode?
No, unfortunately no slave 45/49 mode yet. The firmware supposedly has been written already but not tested yet AFAIK.
Does this mean that the MCK out becomes MCK in when flashing firmware? If so - what version of firmware does have this problem, and is there any version that works as thought?
It is not a problem, it is a feature.
If you check the drop down list of available firmwares in the flash tool you'll see one of them is named "cpld_slave2224". That is the one that enables the slave mode, the rest of the available firmwares work in standard master mode where pin 6 is output.
Jackal, i know that it's a feature that it can take MCK input, but earlier it was talk about the MCK input was through the DSDOE pin or something like that. So this is what makes me confused. Is it an older firmware that does take MCK input on the DSDOE pin, while the cpld_slave2224 fw does take it at the MCK-pin?
Also, i thought i read somewhere that the ES9018 should play DSD without any DSDOE input signal?
Also, i thought i read somewhere that the ES9018 should play DSD without any DSDOE input signal?
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