adding Digital audio transmitter to B&O CD50

Status
This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.
Well, i like to hold on to the fact that the YM2201 is controlled by a 8.6436Mhz Xtal and the data is clocked out at 44.1Khz with 49bits !
running the CS8406 on the 8.6436Mhz ? 8.6436 / 44100 = 196, this fs divider is not found in CS8406. I run it in slave mode, maybe my problem is that the 11.2896Mhz isn't in sync with the players LRclock... but i think that it might only give a few lost frames.

The missing component is a 3way header, the only other missing 3 way header in the player is sitting next the YM3531 pin 35,36,37. These are SUB/VFSY/RCK... from the "Sub code seperation Q code CRC block".
So they did in fact supply all the digital signals needed for digital out on the player.

Only thing i haven't tryed is to invert all the signals.. :smash:

Best regards

Kim Olesen
 
Hi

Try'ed a few things today. Replaced the Xtal in the 11.2896Mhz OSC with a Coil, and got the PLL in lock, so now the clock's should run correctly. But there is still only noise, so either the CS8406 is dead (don't think it is as delaying the clock makes some music get through the noise), or the data from the YM2201 is crap. Tracing the data output shows that after the 16bit of left adjusted information, the dataout is held high or low through the last 8-9 clock pulses, until LRclock shift's. Will that F*** up the data in the CS8406 ? will it be seen as 24bit data ?


Best regards

Kim Olesen
 
The YM3613 has a SEL pin controlling data input, when low it transmit LSB first it says (not as usual the MSB left adjusted).
 

Attachments

  • sel_hl.gif
    sel_hl.gif
    4.5 KB · Views: 165
Hi

Tryed a "I2S to EIAJ" converter today, setting the CS8406 to I2S mode and delaying the data 2-3-4-5clock cycles. Now i get highly distorted music from my PC speaker. Measured it with a scope, and it looks like a music signal riding on top and bottom of a random square wave.. Also tryed to shift data 8bit's and set the CS8406 to 16bit LSB, but only noise came out. Is the CS8406 expecting 24+24 or 32+32bit ? if 32+32, then shifting data 8 position will not be enough to LSB adjust the data, or what ?

Also tryed feeding the data indput with some clock pulses from the OMCK divider, the is no noise from the soundcard only a DC change.

Only solution i can come up with is that i have to cancel out the random high's/low's after the 16bit data as i think these are accepted by the CS8406 as 24bit data...

Any other ideas ????

Best regards

Kim Olesen
 
Solution ??????

Okay a little experiment...

Used Cooledit to make some 1Khz/10Khz/20Khz sine/square wave files and burned a test cd...

When playing a square wave i could log 4 different 16bit data signals, (0) or (1) bit is last bit when reading data as I2S. when calculating I2S first bit is not used.

1: 0001101111111101(1) = 7165 (14331)
2: 1010010000000010(0) = 41986 (18436)
3: 1001101111111101(1) = 39933 (14331)
4: 0110010000000010(0) = 25602 (51204)


This is not looking as what it takes to make a square signal...

Mirroring the signal....

1: (1)1011111111011000 = 49112 (57324)
2: (0)0100000000100101 = 16421 (8210)
3: (1)1011111111011001 = 49113 (57324)
4: (0)0100000000100110 = 16422 (8211)

This looks more like it, only problem is the offset is not 32768 when Left adjusted. But when using I2S..

57324 - 32768 = 24556
32768 - 8211 = 24557

Does this look correct ?
solution:
49bit Serial data to paralel, latch on LR clock swap the bit's at outputs of latch and into a 49bit P/S... :)


Best regards

Kim Olesen
 
Hi

First shematic of Yamaha YM2201 output to I2S converter, have removed some gates from my test board so this version is not tested yet.

Still working on second schematic of the 8.6436 OSC (LClock2), 11.2896 VCO (modified LClock2), PLL (74HC9046) and CS8406..

:confused: What will be the best for low jitter? Cd-players low jitter 8.6436Mhz OSC controlling a low jitter 11.2896Mhz VCO for the SPDIF transmitter or the SPDIF transmitters low jitter 11.2896Mhz OSC controlling a low jitter 8.6436Mhz VCO for the cd-player (i would vote for the last).

Best regards

Kim Olesen www.micro-io.dk
 

Attachments

  • spdif_ym2201_converter.gif
    spdif_ym2201_converter.gif
    42.3 KB · Views: 243
Interesting thread! I am looking forward to see your PLL solution.

I need to implement a PLL to get 128fs from 64fs, to clock a spdif TX (Crystal CS8402, if I can get it). Do you know of any reference designs or application notes of 4046/9046 ?

BTW, my RME Digi96 soundcard has a 4046 in it, so this must be a good chip.

Best regards,
Alexandre
 
Hi Alexandre

Take a look at Hagtech's dac, he uses the 9046. I have tried exactly this config on my PLL, as vco i used the oscillator part of a LClock2 with a variocap parallel to the trimmer... You only need to divide the 128fs by two and feed it to the 9046, so that it can compare the 64fs and the 128fs/2.
I have finished my schematic and PCB, only need to make the board and mount it... :smash:

Best regards

Kim Olesen
 
Status
This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.