Zoran said:
I think you could connect it in this mode to the decoder chips in the first philips players containing the first chipset (14 bit DAC's)
One could try to connect it there before the digital filter.
I think the data goes from 16 bit no oversampling to 14 bit 4* oversampling by the filter. So get an old working philips and try.
I did not myself, but there is a post here from a while ago discussing this. Find it and ask if the guy tried.
So to your second question: TDA1540 is similar, but that one is mono and 14 bit.
Greetings,
GuidoB
My intension is : somehow to split the L/R digital data and then feed the DAC chip...
To use advantage of split chanel power supplys...
I saw a design by mr Guido B. and that is the great solution of course...)
But I think maybe it is possibile to do the same without the lets say complex
programming of the GAL chip...
I have some AD papers about transfering the I2S to drive the AD1851/AD1856
Also I have some Philips Datasheets about the I2S standard and recomenadations for the recever and transmiter.That is very useful. If someone is interested i can post to forum...
To use advantage of split chanel power supplys...
I saw a design by mr Guido B. and that is the great solution of course...)
But I think maybe it is possibile to do the same without the lets say complex
programming of the GAL chip...
I have some AD papers about transfering the I2S to drive the AD1851/AD1856
Also I have some Philips Datasheets about the I2S standard and recomenadations for the recever and transmiter.That is very useful. If someone is interested i can post to forum...
Zoran said:
In terms of the physical resources required, there is no significant difference between the two methods of creating a balanced dac with the TDA1541A. One can create a balanced I2S signal with three IC's or a single cpld. It would take a similar amount of logic to convert the binary two's complement signal to the complementary offset binary format required by the TDA1541A when in simultaneous data input mode.
There is one advantage to using the simultaneous mode in that the dac will support 8x oversampling.
@ Zoran
I´m very interested if you find a way to use them in differential mode with a given source, let´s say for example i2s.... if it´s simple enough for me.... For now, I prefer wasting my time in building gainclone´s as I need something to feed with my already build dac´s ;-) it get´s boring to listen always to headphones
Thanks!
I´m very interested if you find a way to use them in differential mode with a given source, let´s say for example i2s.... if it´s simple enough for me.... For now, I prefer wasting my time in building gainclone´s as I need something to feed with my already build dac´s ;-) it get´s boring to listen always to headphones
Thanks!
I did not see from the datas of TDA 1541A
that the data is nessesey to be oversmpled using chip im simultaneous L/R mode...My intension is to use the chip in non-oversampled regime and un-balanced audio output...
for now.
I simple think :
In common I2S mode that is happening :
latch going low (prior one clock to MSB of the word N of datas)
then word going to be read by Left part
of DAC
Right part of dac doing nothing for the same period of time. Then latch going Hi and word N+1 going to be read by the Right part of DAC, for that time Left part stays inactive...I will try certanly one middle solution: to use Q out for left ch. of one DAC chip; and -Q for right ch. of second chip and after conversion put together Iouts from L1+R2 and R1+L2...Flip-Flop is clocked by the SCLK...
that the data is nessesey to be oversmpled using chip im simultaneous L/R mode...My intension is to use the chip in non-oversampled regime and un-balanced audio output...
for now.
I simple think :
In common I2S mode that is happening :
latch going low (prior one clock to MSB of the word N of datas)
then word going to be read by Left part
of DAC
Right part of dac doing nothing for the same period of time. Then latch going Hi and word N+1 going to be read by the Right part of DAC, for that time Left part stays inactive...I will try certanly one middle solution: to use Q out for left ch. of one DAC chip; and -Q for right ch. of second chip and after conversion put together Iouts from L1+R2 and R1+L2...Flip-Flop is clocked by the SCLK...
I2S to simultaneous mode converter with L/R differential split for TDA1541A
Hi Guys,
I was looking into doing the same thing, so that I can uses 2 * TDA1541A in a balanced configuration. A few weeks ago I had designed the circuit, but never got the chance to try it out (and I won’t for a while), but here it is, works in theory/simulation. I think it should be fine, but try it out and let me know. Comments, suggestions, questions, all welcome.
About the circuit
---------------------
Well it’s not that hard to work out, it looks like it’ll take about 8 IC packages to implement, so not all that bad I guess… The top part of the circuit U19/20/21 convert the data from two’s complement to offset binary. U18, makes sure that the glitch produced by the logic that precede it, is not visible to external circuitry. The glitch is not a problem, as it occurs on the non-data-clocking edge of the clock (BCK). In fact it is possible to simplify the circuit if you let the glitch pass through, and this is ok if you’re going to feed the output straight into the TDA1541As. But this’ll get ugly if you’re re-clocking the data using a high-speed clock before feeding it into the DACs. So leave it as it is, there is no glitch.
The rest I’m sure you can work out, or just ask…
If you try it out, let me know how it goes… have fun
Hi Guys,
I was looking into doing the same thing, so that I can uses 2 * TDA1541A in a balanced configuration. A few weeks ago I had designed the circuit, but never got the chance to try it out (and I won’t for a while), but here it is, works in theory/simulation. I think it should be fine, but try it out and let me know. Comments, suggestions, questions, all welcome.
About the circuit
---------------------
Well it’s not that hard to work out, it looks like it’ll take about 8 IC packages to implement, so not all that bad I guess… The top part of the circuit U19/20/21 convert the data from two’s complement to offset binary. U18, makes sure that the glitch produced by the logic that precede it, is not visible to external circuitry. The glitch is not a problem, as it occurs on the non-data-clocking edge of the clock (BCK). In fact it is possible to simplify the circuit if you let the glitch pass through, and this is ok if you’re going to feed the output straight into the TDA1541As. But this’ll get ugly if you’re re-clocking the data using a high-speed clock before feeding it into the DACs. So leave it as it is, there is no glitch.
The rest I’m sure you can work out, or just ask…
If you try it out, let me know how it goes… have fun
Attachments
Re: I2S to simultaneous mode converter with L/R differential split for TDA1541A
Was curious so I built it. Does not do what it is supposed to, though from its description, I must admit, I am not absolutely sure how it is supposed to do what it is supposed to do. What it does do very well is create a burst serial clock with a two cycle offset between them. No simultaneous data and no conversion to offset binary.
rah said:Hi Guys,
I was looking into doing the same thing, so that I can uses 2 * TDA1541A in a balanced configuration. A few weeks ago I had designed the circuit, but never got the chance to try it out (and I won’t for a while), but here it is, works in theory/simulation. I think it should be fine, but try it out and let me know. Comments, suggestions, questions, all welcome.
About the circuit
---------------------
Well it’s not that hard to work out, it looks like it’ll take about 8 IC packages to implement, so not all that bad I guess… The top part of the circuit U19/20/21 convert the data from two’s complement to offset binary. U18, makes sure that the glitch produced by the logic that precede it, is not visible to external circuitry. The glitch is not a problem, as it occurs on the non-data-clocking edge of the clock (BCK). In fact it is possible to simplify the circuit if you let the glitch pass through, and this is ok if you’re going to feed the output straight into the TDA1541As. But this’ll get ugly if you’re re-clocking the data using a high-speed clock before feeding it into the DACs. So leave it as it is, there is no glitch.
The rest I’m sure you can work out, or just ask…
If you try it out, let me know how it goes… have fun
Was curious so I built it. Does not do what it is supposed to, though from its description, I must admit, I am not absolutely sure how it is supposed to do what it is supposed to do. What it does do very well is create a burst serial clock with a two cycle offset between them. No simultaneous data and no conversion to offset binary.
Unfortunately, I don’t have the time to work on it atm, as soon as I do, I’ll get into it and see what’s happening. Till then maybe someone else may wanna think about it. Here is a simplified circuit that I did (with the glitch), and the output waveforms, this is what I had simulated. The only difference between this one and the other one (above), is that the other one delays the data and clock bursts by one BCK cycle.
OOPS, and it should also be delaying RLE and LLE by one cycle! That’s probably why it’s not working, err…
The timings on this circuit are correct, and the relative timing of RLE, LLE, LCK, RCK, and LDATA / RDATA should be like this:
Zoran,
That circuit from I2SBUS.pdf can also be used to do this, ie. L+/L- and R+/R- output. There is another circuit in that datasheet, called the ‘transmitter’. If you make a ‘receiver’ and receive the I2S, you can feed the parallel RIGHT and LEFT data into 2 x Transmitters, which will pack in the data into 2 x I2S streams, which you can feed into 2 x TDA1541As.
OOPS, and it should also be delaying RLE and LLE by one cycle! That’s probably why it’s not working, err…
The timings on this circuit are correct, and the relative timing of RLE, LLE, LCK, RCK, and LDATA / RDATA should be like this:
Zoran,
That circuit from I2SBUS.pdf can also be used to do this, ie. L+/L- and R+/R- output. There is another circuit in that datasheet, called the ‘transmitter’. If you make a ‘receiver’ and receive the I2S, you can feed the parallel RIGHT and LEFT data into 2 x Transmitters, which will pack in the data into 2 x I2S streams, which you can feed into 2 x TDA1541As.
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Hi
Rah could You ehplain to me
which bit or word at the digital side is resposibile for the balanced out at the
analog side...
By the way in which software You done these simulations..? They look very nice...
Obviously I have to use the simulations as well to work a litlle bit about that idea
transmiter-recever by philips...
Thanks
Rah could You ehplain to me
which bit or word at the digital side is resposibile for the balanced out at the
analog side...
By the way in which software You done these simulations..? They look very nice...
Obviously I have to use the simulations as well to work a litlle bit about that idea
transmiter-recever by philips...
Thanks
As I can see :
only in simultaneous mode
we can achieve the "real time"
conversion of booth chanels...
That is can be seen from datasheets of
TDA1541A...where in that mode
MSB/LSB of one chanel fits in S-clock time line with MSB/LSB of another chanel.
In all other cases we have a the "time hole" of one word-leght or 16 S-clock cycles..?
Is that right? Basing of that facts the compleat spliting of chanels Power suplys
and the digital data inputs can be relise only in that mode ?
Second :
Maybe that "time holes" coused bu the latching chanels from WS is important for the sound image? Becouse of sort of "resting" one half of the chip?
maybe the simultaneous bus wil somehow saturate the chip implicating bad audio result ?
only in simultaneous mode
we can achieve the "real time"
conversion of booth chanels...
That is can be seen from datasheets of
TDA1541A...where in that mode
MSB/LSB of one chanel fits in S-clock time line with MSB/LSB of another chanel.
In all other cases we have a the "time hole" of one word-leght or 16 S-clock cycles..?
Is that right? Basing of that facts the compleat spliting of chanels Power suplys
and the digital data inputs can be relise only in that mode ?
Second :
Maybe that "time holes" coused bu the latching chanels from WS is important for the sound image? Becouse of sort of "resting" one half of the chip?
maybe the simultaneous bus wil somehow saturate the chip implicating bad audio result ?
Rah,
Still no simultaneous data.
Zoran,
Whatever mode the data arrives in, it is converted simultaneously. Serial data is loaded into the L and R data registers and both channels are converted on the first rising edge of bitclock after the falling edge of wordclock. So long as the L and R data registers are loaded before the conversion point the dac does not care and that is why the TDA1541A will work with bitclock frequencies of between 32Fs and 64Fs.
While not wishing to dissuade anyone from seeking to use the simultaneous mode, it has to be noted that it is a dead end in that it is only applicable to the TDA1541x. The L/L- and R/R- mode is far more useful in that it is applicable to a number of dac chips.
Still no simultaneous data.
Zoran,
Whatever mode the data arrives in, it is converted simultaneously. Serial data is loaded into the L and R data registers and both channels are converted on the first rising edge of bitclock after the falling edge of wordclock. So long as the L and R data registers are loaded before the conversion point the dac does not care and that is why the TDA1541A will work with bitclock frequencies of between 32Fs and 64Fs.
While not wishing to dissuade anyone from seeking to use the simultaneous mode, it has to be noted that it is a dead end in that it is only applicable to the TDA1541x. The L/L- and R/R- mode is far more useful in that it is applicable to a number of dac chips.
rfbrw,
Did you try the second circuit ? Did you get those waveforms ? Checked that the TDA1541A was in simultaneous mode ? ( pin 27 connection) ? You must be getting something out, with all those signals going in? or is it silent?
This is how it was meant to function, maybe someone can see the problem. From the TDA1541A datasheet:
“When input OB/TWC input is connected to VDD1 the two channels of data (L/R) are input simultaneously via DATA L and DATA R, accompanied with BCK and a latch-enable input (LE). With this mode selected the data must be in offset binary. "
If you look at the timing data below, you’ll see that LE goes high after the LSB has been clocked in, and loads the data from the shift register used to receive it internally. Now from I2S, we are able to select left/right data based on WS. So for example if WS is low, we select left, and feed I2S - BCK to LCK (the burst wave). With it goes the data. If the LCK clock isn’t ticking, it won’t load any data in, that’s why it remains low (after the falling clock-in edge), at this time the right one takes over. Now with I2S, WS changes before the LSB is clocked in (rising edge) , with the simultaneous mode we want the latch to open after the LSB has been clocked in (on the falling edge), so the WS signal is delayed appropriately.
The timing chart below shows that LE must close before the data for the next word is clocked in (starting with the MSB), and this is fine, cause the clock LCK/RCK don’t tick in the period where RLE /LLE is high (latch open) and no data is clocked in. Before the clock starts up again, LLE or RLE close, so that the data may be loaded.
As for the two’s complement to offset binary conversion, this can simply be done by inverting the MSB of each word. When WS on the I2S bus changes, the next rising edge of BCK is the LSB of the pervious word, and on the rising edge after that, is the MSB of the new word. We use WS and a few D-F/F to find the MSB, ie. a signal that goes high when the MSB of a word is present in the stream. And, pass the DATA and the find-MSB signal through a XOR gate. The XOR gate will invert the DATA when the find signal is high, therefore inverting the MSB, doing tow’s complement to offset binary conversion.
That was how it is suppose to work, any ideas ?
Wait a sec, I have one!
Does WS on I2S change exactly on the falling edge just before the rising edge which clocks in the LSB?
'rah' check the data sheet.... errr! NO. Carefully looking at it again T_HD;WS = 0 and T_SU;WS = 32ns !
If you can see where I've stuffed up, then try to fix it (it should be easy), my simulation I2S is wrong, WS doesn't change like that.
I'll post a fix later... err..
Zoran,
That schematic is done on SIMetrix, unfortunately the demo version has a part limit on simulation. Still a nice program to try things in..
Did you try the second circuit ? Did you get those waveforms ? Checked that the TDA1541A was in simultaneous mode ? ( pin 27 connection) ? You must be getting something out, with all those signals going in?
or is it silent? This is how it was meant to function, maybe someone can see the problem. From the TDA1541A datasheet:
“When input OB/TWC input is connected to VDD1 the two channels of data (L/R) are input simultaneously via DATA L and DATA R, accompanied with BCK and a latch-enable input (LE). With this mode selected the data must be in offset binary. "
If you look at the timing data below, you’ll see that LE goes high after the LSB has been clocked in, and loads the data from the shift register used to receive it internally. Now from I2S, we are able to select left/right data based on WS. So for example if WS is low, we select left, and feed I2S - BCK to LCK (the burst wave). With it goes the data. If the LCK clock isn’t ticking, it won’t load any data in, that’s why it remains low (after the falling clock-in edge), at this time the right one takes over. Now with I2S, WS changes before the LSB is clocked in (rising edge) , with the simultaneous mode we want the latch to open after the LSB has been clocked in (on the falling edge), so the WS signal is delayed appropriately.
The timing chart below shows that LE must close before the data for the next word is clocked in (starting with the MSB), and this is fine, cause the clock LCK/RCK don’t tick in the period where RLE /LLE is high (latch open) and no data is clocked in. Before the clock starts up again, LLE or RLE close, so that the data may be loaded.
As for the two’s complement to offset binary conversion, this can simply be done by inverting the MSB of each word. When WS on the I2S bus changes, the next rising edge of BCK is the LSB of the pervious word, and on the rising edge after that, is the MSB of the new word. We use WS and a few D-F/F to find the MSB, ie. a signal that goes high when the MSB of a word is present in the stream. And, pass the DATA and the find-MSB signal through a XOR gate. The XOR gate will invert the DATA when the find signal is high, therefore inverting the MSB, doing tow’s complement to offset binary conversion.
That was how it is suppose to work, any ideas ?
Wait a sec, I have one!
Does WS on I2S change exactly on the falling edge just before the rising edge which clocks in the LSB?
'rah' check the data sheet.... errr! NO. Carefully looking at it again T_HD;WS = 0 and T_SU;WS = 32ns !
If you can see where I've stuffed up, then try to fix it (it should be easy), my simulation I2S is wrong, WS doesn't change like that.
I'll post a fix later... err..
Zoran,
That schematic is done on SIMetrix, unfortunately the demo version has a part limit on simulation. Still a nice program to try things in..
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