I didn't see their schematics or read what they have. On their product they just say:
"The foundation of the DAC3.5VB mkII is our jitter-eliminating Master Reference Ultra-Clock circuitry that ensures that jitter from any source is reduced below the audible threshold."
and
"...features a class leading 126dB dynamic range with our proprietary low noise digital to analog convertor core."
Sorry, for me that is just a redflag for marketing bull...
To add to the discussion... when I was working on a broadcast design a number of years back, I built a jitter reduction test setup and evaluated a bunch of ASRCs with it. ASRCs have a sample rate tracking loop - any jitter above the corner frequency of this loop is rejected, and below the loop it gets encoded into the data. We don't want the latter at all, so I built a setup that allowed me to look for "encoded jitter".
Test setup was this:
- DSP chip running a DDS algorithm generated a pure sine wave and fed it out an I2S port, to feed the ASRC input. Dynamic range of the sine wave was ~140dB, pretty much the limits of 24 bit encoding.
- The ASRC input clock was generated with a DDS chip, allowing me to modulate 'jitter tones' into it. This was done by modulating the DDS chip with the DSP chip.
- ASRC master clock was a decent 24.576MHz oscillator, and the ASRC output frequency was 96KHz, derived from the same clock.
- ASRC output fed a CS8404 DIT chip - I used AES/EBU as the output format and fed it into an Audio Precision SYS-2522.
- Audio Precision software was used to measure any jitter tones that "FM modulated" the sine coming from the DSP, and also to look for THD on the sine. Timing of the AES/EBU signal wasn't used for analysis, only the data carried on it.
- Three separate power supplies were used for the DSP/DDS, ASRC clock/output and AES line driver to make sure everything was nicely decoupled from each other.
I can't post any detailed results or any schematics of the jig (changed jobs, don't have access to the information anymore, plus the whole NDA thing) but here's the jist of everything:
- Parts tested: AD1895/1896, SRC4382/4392, SRC4190/4192.
- AD1895/AD1896 worked great. Both had equivalent jitter reduction, AD1896 had lower THD.
- SRC4382/SRC4392 had great jitter reduction. SRC4392 had less THD, and performance was pretty much identical to the AD1896.
- SRC4190 worked really well also, results pretty much identical to the AD1895. Pinout/performance/characteristics are all the same, I wouldn't be surprised if they have the same die inside.
- SRC4192 wasn't so great. Better THD than 4190 but seemed to have a higher rate tracking loop, and jitter at frequencies well into the sub-bass range were making it into the output.
In conclusion:
- SRC4392/AD1896 have pretty much identical performance - no point in criticizing anyone for choosing one chip over the other.
- AD1895/SRC4190/SRC4382 have excellent jitter performance but marginally worse THD performance. If you're running redbook audio through the chip, I can pretty much say for sure that any THD introduced by the ASRC will be lost in the dither of the CD that you're listening to.
- I would not recommend the SRC4192 unless you put good quality clocks on both sides of it, eg. you're using it as a 44.1/48 translator in an embedded design or something. I wouldn't feed a 4192 with a SPDIF receiver.
Test setup was this:
- DSP chip running a DDS algorithm generated a pure sine wave and fed it out an I2S port, to feed the ASRC input. Dynamic range of the sine wave was ~140dB, pretty much the limits of 24 bit encoding.
- The ASRC input clock was generated with a DDS chip, allowing me to modulate 'jitter tones' into it. This was done by modulating the DDS chip with the DSP chip.
- ASRC master clock was a decent 24.576MHz oscillator, and the ASRC output frequency was 96KHz, derived from the same clock.
- ASRC output fed a CS8404 DIT chip - I used AES/EBU as the output format and fed it into an Audio Precision SYS-2522.
- Audio Precision software was used to measure any jitter tones that "FM modulated" the sine coming from the DSP, and also to look for THD on the sine. Timing of the AES/EBU signal wasn't used for analysis, only the data carried on it.
- Three separate power supplies were used for the DSP/DDS, ASRC clock/output and AES line driver to make sure everything was nicely decoupled from each other.
I can't post any detailed results or any schematics of the jig (changed jobs, don't have access to the information anymore, plus the whole NDA thing) but here's the jist of everything:
- Parts tested: AD1895/1896, SRC4382/4392, SRC4190/4192.
- AD1895/AD1896 worked great. Both had equivalent jitter reduction, AD1896 had lower THD.
- SRC4382/SRC4392 had great jitter reduction. SRC4392 had less THD, and performance was pretty much identical to the AD1896.
- SRC4190 worked really well also, results pretty much identical to the AD1895. Pinout/performance/characteristics are all the same, I wouldn't be surprised if they have the same die inside.
- SRC4192 wasn't so great. Better THD than 4190 but seemed to have a higher rate tracking loop, and jitter at frequencies well into the sub-bass range were making it into the output.
In conclusion:
- SRC4392/AD1896 have pretty much identical performance - no point in criticizing anyone for choosing one chip over the other.
- AD1895/SRC4190/SRC4382 have excellent jitter performance but marginally worse THD performance. If you're running redbook audio through the chip, I can pretty much say for sure that any THD introduced by the ASRC will be lost in the dither of the CD that you're listening to.
- I would not recommend the SRC4192 unless you put good quality clocks on both sides of it, eg. you're using it as a 44.1/48 translator in an embedded design or something. I wouldn't feed a 4192 with a SPDIF receiver.
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