The technical papers I read referred to at low DEM fs you would need very large impractical cap' values on the decoupling pins to filter the ripple. Though the paper also discussed an option using the same clock fs for all stages in the divider and the timing error. The tda1541a datasheet uses all 100nf I believe. ECDesigns directed me to Td1540 datasheet where they show a divide by 2 on the decoupling caps. I don't know if the tda 1541a is the same but it might just be the practical implementation.
That said I am coming to the conclusion that it isn't possible to push the DEM fs higher after reading ECDesigns, and other posters.
Arcam in their black box did tinker running a 680pf oscillator, and varying the decoupling caps. They also ran the tda1541a at -6.2V....
I must get my black box out of storage. edit: It did not sound that great to be honest.
http://www.diyaudio.com/forums/digital-source/60934-arcam-delta-black-box1-mods-5.html#post2328437
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arcam mods
ash_dac
In case you did not see it, there is a very good record of mods made to arcam alpha at
http://www.diyaudio.com/forums/digital-source/167068-arcam-alpha-mods.html
Schematic of black box and alpha have many similarities. Shame to have black box in storage.
ash_dac
In case you did not see it, there is a very good record of mods made to arcam alpha at
http://www.diyaudio.com/forums/digital-source/167068-arcam-alpha-mods.html
Schematic of black box and alpha have many similarities. Shame to have black box in storage.
I just measured the voltages at the DEM pins:
Pin 13, 18, 12, 19: -7.4 ... -7.6 V
Pin 11, 20, 10, 21: -5.2 ... -5.5 V
Pin 9, 22, 8, 23: -3.9 V
Pin 7, 24: - 3.5 V
Based on the diagram of the DEM switch principle I conclude in the following pin assignment:
Bit 16 - pins 13, 18
Bit 15 - pins 12, 19
Bit 14 - pins 11, 20
Bit 13 - pins 10, 21
Bit 12 - pins 9, 22
Bit 11 - pins 8, 23
To passive divider (Bits 10 to 1) - pins 7, 24
I also measured the ripple at each pins by removing the external capacitors (using C = 1.5 nF resulting in fDEM = 60 kHz). Each pin showed a four step pattern repeating, the length of each step was one DEM sample.
Hi, -ecdesigns-
At given thread we discuss working of 1541 without oversampling (NOS). Work with oversampling – a separate subject.
Hi, studiostevus
Apropos, in TDA1541 no resistor, which it is necessary to adjust. You unattentive read the article.
Why fDEM = 2fWS? fDEM = 0,5fWS!
Apropos, in TDA1541 no resistor, which it is necessary to adjust. You unattentive read the article.
Hi, brubeck,
You not rule. DEM averages DC constituting of bit current. The capacitor filters AC constituting of this current, but he can not average DC constituting because capacitor at direct currents does not operate. So capacitor can not operate instead of DEM.
You not rule. DEM averages DC constituting of bit current. The capacitor filters AC constituting of this current, but he can not average DC constituting because capacitor at direct currents does not operate. So capacitor can not operate instead of DEM.
You rule, oshifis.
Here is table of my measurements, as well as my reconstruction of the internal scheme of TDA1541.
Very interesting measurements. But my measurement and the analysis of the DEM circuit operation shows pulse width = 1 / fDEM on all pins. A pattern of four such pulses each having slightly different amplitude repeats itself. Does Частота пульсаций mean the ripple frequency? Did you measure it, or theoretically concluded?
Hi oshifis,
I also measured same ripple frequency on all active divider outputs with decoupling cap removed.
Article about DEM circuit shows two different frequencies as SSerg indicated.
f for single active divider output and f/2 for paralleled active divider outputs.
f/2 occurs in theory when a specific combination of tolerances is present on both paralleled outputs. I never measured this in practice, and I measured many TDA1541A chips.
After filtering, the ripple current should be so low that it has no audible effect at all (far less than 1 LSB).
When jitter on the DEM oscillator is -not- random, it can lead to slowly fluctuating bit current errors on the active divider outputs. These cannot be filtered out by the decoupling cap as it wasn't dimensioned to attenuate ripple frequencies that are much lower than fDEM.
Example, when the DEM frequency is phase modulated with a sine wave of say 50Hz (mains) it translates in a specific distribution of interval timing that in turn results in bit errors that vary with 50Hz pattern. In other words, a low frequency ripple current is generated by DEM oscillator phase modulation. The decoupling caps (100nF typically) are not able to attenuate these low frequencies as they were dimensioned to filter out 150 … 250 KHz ripple only. This would be periodic jitter.
Instead of 50, 60, 100, 120 Hz phase modulation as a result of power supply ripple for example, the DEM oscillator can also be phase modulated by low frequency components (that have too low frequency to be filtered out by the decoupling caps) generated by DATA or L-OUT and R-OUT. This would be deterministic DEM oscillator jitter.
This non-random phase modulation of the DEM oscillator leads to slowly fluctuating bit errors that become audible as the decoupling caps fail to attenuate this low frequency ripple.
I also measured same ripple frequency on all active divider outputs with decoupling cap removed.
Article about DEM circuit shows two different frequencies as SSerg indicated.
f for single active divider output and f/2 for paralleled active divider outputs.
f/2 occurs in theory when a specific combination of tolerances is present on both paralleled outputs. I never measured this in practice, and I measured many TDA1541A chips.
After filtering, the ripple current should be so low that it has no audible effect at all (far less than 1 LSB).
When jitter on the DEM oscillator is -not- random, it can lead to slowly fluctuating bit current errors on the active divider outputs. These cannot be filtered out by the decoupling cap as it wasn't dimensioned to attenuate ripple frequencies that are much lower than fDEM.
Example, when the DEM frequency is phase modulated with a sine wave of say 50Hz (mains) it translates in a specific distribution of interval timing that in turn results in bit errors that vary with 50Hz pattern. In other words, a low frequency ripple current is generated by DEM oscillator phase modulation. The decoupling caps (100nF typically) are not able to attenuate these low frequencies as they were dimensioned to filter out 150 … 250 KHz ripple only. This would be periodic jitter.
Instead of 50, 60, 100, 120 Hz phase modulation as a result of power supply ripple for example, the DEM oscillator can also be phase modulated by low frequency components (that have too low frequency to be filtered out by the decoupling caps) generated by DATA or L-OUT and R-OUT. This would be deterministic DEM oscillator jitter.
This non-random phase modulation of the DEM oscillator leads to slowly fluctuating bit errors that become audible as the decoupling caps fail to attenuate this low frequency ripple.
CD PRO question
Hi guys,
while I'm studying TDA1541 and SAA7324 timing I have a question.
I own 1 CD PRO2M module, 1 TDA1541 S1 and 1 8.4762MHz ultra low phase noise OCXO. I play 44.1/16 bit material only, so I would like to put all in a box to build a simple integrated CD player. I would like to use the same OCXO either for the transport than for the DAC chip. I'll take I2S signal directly from CD PRO to feed TDA1541.
The CD PRO uses SAA7324 as servo/decoder to output I2S; there is a poor 8.4762MHz crystal on the board I want replace with OCXO clock. it seems SAA7324 is configured to provide 2 words of 24 bit at 4fs, so BCK is exactly 8.4672MHz (24*2*4*44.1), so I think I can remove the crystal and inject the clock coming from OCXO.
About TDA1541, I would like to implement it in NOS mode, so my question:
is it right to divide OCXO clock by 4 (2.1168MHz) for DAC chip BCK?
Andrea
Hi guys,
while I'm studying TDA1541 and SAA7324 timing I have a question.
I own 1 CD PRO2M module, 1 TDA1541 S1 and 1 8.4762MHz ultra low phase noise OCXO. I play 44.1/16 bit material only, so I would like to put all in a box to build a simple integrated CD player. I would like to use the same OCXO either for the transport than for the DAC chip. I'll take I2S signal directly from CD PRO to feed TDA1541.
The CD PRO uses SAA7324 as servo/decoder to output I2S; there is a poor 8.4762MHz crystal on the board I want replace with OCXO clock. it seems SAA7324 is configured to provide 2 words of 24 bit at 4fs, so BCK is exactly 8.4672MHz (24*2*4*44.1), so I think I can remove the crystal and inject the clock coming from OCXO.
About TDA1541, I would like to implement it in NOS mode, so my question:
is it right to divide OCXO clock by 4 (2.1168MHz) for DAC chip BCK?
Andrea
Hello Andrea,
it is right to divide OCXO clock by 4 (2.1168MHz) for DAC chip BCK.
If your OCXO has 2 clock outputs use one for the divider by 4 and the other via an inverting/non-inverting buffer for the SAA7324 clock input (do not exceed 3.3V level).
Take care that the SAA7324 doesn't output the I2S-signals with a fixed phase relation
to the 8.4762MHz input clock (there are 3 or 4 posible phases after power up).
So it can happen that you have re-power the CD-Pro until you get a correct audio signal.
it is right to divide OCXO clock by 4 (2.1168MHz) for DAC chip BCK.
If your OCXO has 2 clock outputs use one for the divider by 4 and the other via an inverting/non-inverting buffer for the SAA7324 clock input (do not exceed 3.3V level).
Take care that the SAA7324 doesn't output the I2S-signals with a fixed phase relation
to the 8.4762MHz input clock (there are 3 or 4 posible phases after power up).
So it can happen that you have re-power the CD-Pro until you get a correct audio signal.
Josi1,
thanks for reply.
Andrea
thanks for reply.
Unfortunately my OCXO has only one output, so I have to use it for both SAA7324 and TDA1541.
That could be a little problem.. I see 7324 has a power-on reset input (pin 38), so I should reset it until I detect a correct audio signal at the output. Any idea?
Andrea
Hi to all,
Here are some explanations towards my table and table itself translated in English.
The measurements are executed for two samples of the microcircuits (the conditional number 1 and 2). The frequency f – a frequency of the switching DEM-cell. For built-in multivibrator and capacity of the external capacitor 470 pF she forms 200 - 250 kHz.
Sensibly expect that for pins 8, 9 (23, 22) filtering resistances are equal, in the same way either as for pins 10, 11 (20, 21). The difference of the voltages at pins 8, 9 (23, 22) and 10, 11 (20, 21) allows to estimate the resistance of filtering resistors. This difference for greater precision is measured at the other limit of the measurements. The result was provided in table.
After uncomplicated calculations we get that for pins 8, 9, 22, 23 filtering resistances are 1,0 kOm, but for pins 10, 11, 20, 21 – 1,6 kOm.
Here are some explanations towards my table and table itself translated in English.
The measurements are executed for two samples of the microcircuits (the conditional number 1 and 2). The frequency f – a frequency of the switching DEM-cell. For built-in multivibrator and capacity of the external capacitor 470 pF she forms 200 - 250 kHz.
Sensibly expect that for pins 8, 9 (23, 22) filtering resistances are equal, in the same way either as for pins 10, 11 (20, 21). The difference of the voltages at pins 8, 9 (23, 22) and 10, 11 (20, 21) allows to estimate the resistance of filtering resistors. This difference for greater precision is measured at the other limit of the measurements. The result was provided in table.
After uncomplicated calculations we get that for pins 8, 9, 22, 23 filtering resistances are 1,0 kOm, but for pins 10, 11, 20, 21 – 1,6 kOm.
Hi, studiostevus,
The required capacity depends from resistance of the resistor not only, but as well as from ripple frequency and values of the bit currents.
Coming out of these values, possible estimate the caps capacity correlation required for alike filtering actions for different bits.
The required capacity depends from resistance of the resistor not only, but as well as from ripple frequency and values of the bit currents.
Coming out of these values, possible estimate the caps capacity correlation required for alike filtering actions for different bits.
Note that a current generator is different from a resistor in that the voltage drop is not proportional to the resistance... So concluding to the internal resistance from the measured voltage drop can be misleading. I recommend a dynamic measurement method instead, e.g. by measuring the RC time constant. It can also be measured by applying an external adjustable current source and measure the variation of voltage caused by a small current change.
That's a possibility indeed, but forgive my ignorance... What would be the point, as long as the filtering is sufficient to filter out the switching ripple, no?
The only further benefit i can think of is aligning the rc filter's phase shifts between the different bits (1-16)... Not sure what the benefit of that would be though (can't hurt for sure)
Hi, oshifis
My estimation of the resistance is not perfect, but it is enough motivated.
Call attention that I compare the voltages for resistors within one and same DEM cells; they get the current from one and same current generator, so I factor out current generator.
My estimation of the resistance is not perfect, but it is enough motivated.