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Old 17th January 2012, 04:18 PM   #4151
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Quote:
In the MK9 I am experimenting with different JFETs and MOSFETs, JFETs require negative bias voltage, MOSFETs positive bias voltage.

The effects of TDA1541A output compliance on output signal THD depends on the application.

Second picture shows oscillograms of the JFET current buffer.

Oscillograms show effect of varying DC level on DAC output. With this circuit I can vary DC level by changing JFET gate voltage (source voltage then "follows").
Good. Now we need a current buffer fot the output of the humble TDA1543...I don't remember seing any... As it has only positive supply, I imagine Mosfet would be ideal...

Thanks.
M.
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Old 17th January 2012, 06:21 PM   #4152
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Hi maxlorenz,

Quote:
Good. Now we need a current buffer fot the output of the humble TDA1543...I don't remember seing any... As it has only positive supply, I imagine Mosfet would be ideal...
TDA1543 output circuit is different from TDA1541A and needs no current buffer.

I attached schematic of a TDA1543 DAC with DC-coupled outputs and passive I/V conversion.

This is the best performing (and easiest to build) TDA1543 circuit I designed so far (tested on MK9 prototype setup with latest timing module).

R1, R2, D1 ... D6 are WS / DATA limiters (1.8Vpp).

C1 is a 1uF 1210 SMD film cap soldered directly to TDA1543 pins 4 and 5 as close to the plastic housing as possible.

R3 and R4 are passive I/V resistors that offer approx. 0.0025 * 820 = 2.05Vpp output signal.

P1 is passive I/V resistor bias voltage (adjust to 3.2V).

P2 provides DC-coupled outputs (no coupling cap required). Adjust P2 for lowest DC offset on R and L outputs. This would give around 2.2V on the wiper of P2.

TDA1543 requires a super clean 5V power supply (balanced or battery power supply) and ultra low jitter BCK signal with white noise residual jitter spectrum.
Attached Images
File Type: jpg 1543.jpg (45.2 KB, 2401 views)

Last edited by -ecdesigns-; 17th January 2012 at 06:28 PM.
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Old 17th January 2012, 06:53 PM   #4153
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Wow... didn't know you're also still experimenting with TDA1543 in the background! How does it sound compared to 1541a?

Is there any sight on revised mk9+psu schematic yet (pretty please of course). The components I bought for building mk8 are sitting here unused
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Old 17th January 2012, 10:59 PM   #4154
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Quote:
TDA1543 output circuit is different from TDA1541A and needs no current buffer.

I attached schematic of a TDA1543 DAC with DC-coupled outputs and passive I/V conversion.
Thank you!

I had also that idea of soldering directly the cap to the power and G pins.
Very interesting concept. I shall try it soon.
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Old 18th January 2012, 12:26 PM   #4155
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ECDesigns, what power supply do you feed the 1543? Also, how do you get ultra low jitter BCK signal with white noise residual jitter spectrum?
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Old 19th January 2012, 07:14 AM   #4156
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Hi Dr.H,

Quote:
ECDesigns, what power supply do you feed the 1543? Also, how do you get ultra low jitter BCK signal with white noise residual jitter spectrum?
The TDA1543 is powered by the +5V TDA1541A supply. This consists of a balanced capacitance multiplier followed by a balanced filtered-buffered zener regulator.

I use slaved integrated source (SD-transport). This eliminates S/PDIF and USB source issues alltogether. So I "only" have to focus on masterclock and connected circuit properties.

By integrating CCS / shunt voltage regulator, masterclock, sine to square conversion and division on a miniature timing module (12mm x 35mm x 5mm) it is easier to maintain reproducible extreme low jitter and residual jitter spectrum.
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Old 19th January 2012, 08:43 AM   #4157
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Thanks ecdesigns, you've bee a generous fount of knowledge!

I'm keen to build a couple of your balanced designs as per schematics you've posted earlier. Will report here, juts have to find the time...

I've slaved a PCM63 based to a "Shigaclone" and liked the result-sharper images, lower noise floor.

How would one slave a CS8412-1543 NOS dac to a transport?
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Old 19th January 2012, 02:13 PM   #4158
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Hi Dr.H

Quote:
I've slaved a PCM63 based to a "Shigaclone" and liked the result-sharper images, lower noise floor.
How would one slave a CS8412-1543 NOS dac to a transport?
If I am correct the Shigaclone only outputs S/PDIF. This signal is derived from the Sanyo LC78601 chip (pin 29). So one is stuck with S/PDIF only.

I suggest to use a Wolfson WM8804 receiver with external crystal, this one for example:

The S/PDIF Transceiver Module

CS8412 isn't really a good S/PDIF receiver chip with 200ps rms typical PLL clock jitter plus interlink plus source jitter.

WM8804 datasheet indicates typical 50ps rms PLL jitter. If I am correct source jitter is attenuated by means of reclocking with an on-chip crystal oscillator.

TDA1543 uses BCK for sample timing, so this signal needs to have low jitter.

If I am correct the shigaclone masterclock equals 16.9344 MHz.

You could remove crystal and both caps close to it and get a 16.9344 MHz low jitter masterclock (Tent Labs for example) and place it in the DAC.

Now buffer the masterclock output and feed it to the crystal pad that connects to LC78601 chip pin 61 (X-in).

BCK (2.1168 MHz) can now be derived straight from the masterclock using a synchronous divide by 8 circuit.
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Old 19th January 2012, 02:30 PM   #4159
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Excellent thanks. Just a few quick Q:
1. What buffer would you suggest for the clock?
2. What divider would you suggest?
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Old 19th January 2012, 02:36 PM   #4160
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And also, would I need to invert the clock that is sent back to the transport?
Finally, if the transport starts up without a clock (say the dac is off) is there a risk the transport latches up?

Last edited by Dr.H; 19th January 2012 at 02:40 PM.
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