These are the words of John at post 6116 explaning the glue logic for this setup :
"Back to the Decoder circuit. I attached a schematic of a decoder I designed for this experiment, it is based on the protocol converter I posted earlier. It looks complicated but it is basically as simple as it gets.
We need to do a few things, sample and hold the MSBs, then loose the LSBs from the serial data that goes into the TDA1541A chips. Mix MSB and data signals together so we get dedicated data signals for each TDA1541A.
We know that the MSB are located immediately after a WS change (I use Left justified format!). So we need to create a trigger signal right at the center of these MSBs. We need 0.5 bit delay for that and that's provided by U1. We need to keep the Left MSB with the Left data and the Right MSB with the right data. So we have to invert the 0.5 bit delay signal for one channel. U4 and U5 sample and hold the MSB for each channel, we use these sampled MSBs in the decoder stage.
Loose the MSB, easier said then done as we can't easily shift the serial data to the left unless we add some more shift registers.
Instead I delayed the window that determines when the output signals are generated in relation to WS. By delaying the window signal by one bit I basically removed the MSBs from the serial bit stream, after I have sampled the MSBs of course.
The output of U2 provides a 1 bit delay and the delayed signal goes to the window generator built around counter U6 and NOR gate U17.
U3 lines up the left channel data so the bits are valid on the falling edge of BCKI (TDA1541A clocks on the falling edge of BCK when configured in the simultaneous mode).
U7 ... U10 line up the Right channel data with the Left channel data so both can be clocked out simultaneously.
U16 gates the bit clock so we have a 16 bit clock burst at just the right time. The window signal enables and disables the continuous BCKI signal.
U13 B and D do the same for the serial data, creating 16 bit data bursts at just the right moment.
U13A, U14, U13C and U15 form a simple AND / OR decoder that extracts DOL-, DOL+, DOR-, and DOR+ signals from the serial data streams."
if there is an error/mistake it will be in these words
.
"Back to the Decoder circuit. I attached a schematic of a decoder I designed for this experiment, it is based on the protocol converter I posted earlier. It looks complicated but it is basically as simple as it gets.
We need to do a few things, sample and hold the MSBs, then loose the LSBs from the serial data that goes into the TDA1541A chips. Mix MSB and data signals together so we get dedicated data signals for each TDA1541A.
We know that the MSB are located immediately after a WS change (I use Left justified format!). So we need to create a trigger signal right at the center of these MSBs. We need 0.5 bit delay for that and that's provided by U1. We need to keep the Left MSB with the Left data and the Right MSB with the right data. So we have to invert the 0.5 bit delay signal for one channel. U4 and U5 sample and hold the MSB for each channel, we use these sampled MSBs in the decoder stage.
Loose the MSB, easier said then done as we can't easily shift the serial data to the left unless we add some more shift registers.
Instead I delayed the window that determines when the output signals are generated in relation to WS. By delaying the window signal by one bit I basically removed the MSBs from the serial bit stream, after I have sampled the MSBs of course.
The output of U2 provides a 1 bit delay and the delayed signal goes to the window generator built around counter U6 and NOR gate U17.
U3 lines up the left channel data so the bits are valid on the falling edge of BCKI (TDA1541A clocks on the falling edge of BCK when configured in the simultaneous mode).
U7 ... U10 line up the Right channel data with the Left channel data so both can be clocked out simultaneously.
U16 gates the bit clock so we have a 16 bit clock burst at just the right time. The window signal enables and disables the continuous BCKI signal.
U13 B and D do the same for the serial data, creating 16 bit data bursts at just the right moment.
U13A, U14, U13C and U15 form a simple AND / OR decoder that extracts DOL-, DOL+, DOR-, and DOR+ signals from the serial data streams."
if there is an error/mistake it will be in these words
.
I checked that text already multiple times. He talks about moving MSB around etc., but MSB does different things depending on the coding scheme: have a look at the table I posted in #8296 and you will see what I mean. Maybe you can study my project and put together simulations like I did to see what happens to the individual bits when they travel through the glue logic...
Where do I collect my prize?Congratulation you won the world useless guy price
Consider this statement from your holy text, post #6116
With signed magnitude we usually have two identical DACs. One handles the positive signal halve only, the other handles the negative signal half only.
In others words 4ma for positive half and 4ma for the negative. Here on planet earth that means 4ma for the whole waveform.
But your text also claims this
full scale current doubles to 8mA
Where does the extra 4ma come from ?
BCKO has 16 cycles and DOx all have 16 bits.
Face facts. You cannot convert 17 bits with a dac that has a 16 bit input register.
For a dose of SM reality, try the PCM1702 datasheet.
With signed magnitude we usually have two identical DACs. One handles the positive signal halve only, the other handles the negative signal half only.
In others words 4ma for positive half and 4ma for the negative. Here on planet earth that means 4ma for the whole waveform.
But your text also claims this
full scale current doubles to 8mA
Where does the extra 4ma come from ?
BCKO has 16 cycles and DOx all have 16 bits.
Face facts. You cannot convert 17 bits with a dac that has a 16 bit input register.
For a dose of SM reality, try the PCM1702 datasheet.
He is trying to use two 16bit DACs together to double the resolution up to 17 bits. The outputs of the 2 DACs are added together, hence they say it makes 8ma. The glue logic for splitting the data stream into the required parts was discussed in this thread, but no one has managed to get it working yet - and I thought this might have to do with the data format (COB vs. 2s compliment)...
You can tie the outputs together without doubling the current. It depends on when the dacs convert. From his own words he is trying to copy the Burr Brown SM process but that isn't what BB do. The BB process creates an actual increase in wordlength. It is probably possible to recreate the BB SM process on a TDA1541 but not like this.
If you know about logic you can have a look at the schematic and explanation at post 6116 , this is the one I made , this will be a massive help for me and maybe other people
I just found another hint at the problem, see #7069!
in this post John said it ad been tested , but il does not said if it was with music and stereo mode
the issue they found was for the I2S version
after having solve their problems it seems that the I2S logic converter is now working , see Koldby return at post 7079
from what I saw , it seems that there is something missing on booth channel at the logic board output , because when I set the input on mono mode it works fine , time is now to find what is missing , why and how to fix that issue
tomorrow I will make some more testing with the logic board and I will share the result , may someone see what is wrong
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the issue they found was for the I2S version
after having solve their problems it seems that the I2S logic converter is now working , see Koldby return at post 7079
from what I saw , it seems that there is something missing on booth channel at the logic board output , because when I set the input on mono mode it works fine , time is now to find what is missing , why and how to fix that issue
tomorrow I will make some more testing with the logic board and I will share the result , may someone see what is wrong
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My dear, you need to look at the table I posted in #8296 and understand the difference between 2s complement and offset binary in order to be able to make sure you get it right. It means MSB has the opposite value, whereas with I2S vs. left justified the MSB is at a different position (see attached picture). Both must be correct in order to get it work - and that is independent from the version of the glue logic circuit you use. Not to mention that the TDA1541A needs to be in the appropriate mode as well.
The easiest way is to find out which sorce John used to feed his glue logic: was it really a DIR9001? I say it again: I use a PMD100 and I can tell it works. But as I said for simultaneous mode I set the PMD100 to output COB format.
If you say you get good sound in mono mode it seems that you set the TDA1541A into a different mode: only simultaneous mode expects offset binary, the other modes work with 2s complement.
The easiest way is to find out which sorce John used to feed his glue logic: was it really a DIR9001? I say it again: I use a PMD100 and I can tell it works. But as I said for simultaneous mode I set the PMD100 to output COB format.
If you say you get good sound in mono mode it seems that you set the TDA1541A into a different mode: only simultaneous mode expects offset binary, the other modes work with 2s complement.
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As per post 6080 and 6110 John used the DIR9001 set left justified and the TDA' are set in simultaneous mode ( pin 27 at -5v ) , this is how my setup is made too
the table 8296 does not mean anything for me , as I said before I am not an digital skilled guy , I am just trying to make this stuff working
and the help I am asking is for that purpose only , all the documents/infos are on hand so If someone is willing to help he's welcome
can't say more
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the table 8296 does not mean anything for me , as I said before I am not an digital skilled guy , I am just trying to make this stuff working
and the help I am asking is for that purpose only , all the documents/infos are on hand so If someone is willing to help he's welcome
can't say more
.
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Your diagram shows a different situation: your diagram uses half of one DAC for the positive wave and half of the other DAC for the negative half.
The intended 17bit DAC uses the 4mA of one DAC for the positive half of the wave and the other DAC for the negativ half. Both DACs add together and provide a total of 8mA.
The intended 17bit DAC uses the 4mA of one DAC for the positive half of the wave and the other DAC for the negativ half. Both DACs add together and provide a total of 8mA.
You cannot do that because you cannot you use all 65536 steps to represent one half wave. You would need a straight binary dac for that. Whether BTC or COB, the dac will not increment from 0111 1111 1111 1111 (32767) to 1000 0000 0000 0000 (32768). It will wrap around back to the opposite polarity. Unlike a straight binary dac, the MSB has no numerical value. It is a signifier for either negative or positive.
It's possible to add DACs just like batteries on top of each other regardless of internal architecture, as long as the analog outputs are added correctly together and the digital data is prepared properly. This is discussed in this thread since a couple of thousands posts ;-)
Of course MSB has a value: either one or zero, as all other bits in the stream. MSB is just the first piece of information. In some formats it's used to define the polarity, but not in all formats...
Of course MSB has a value: either one or zero, as all other bits in the stream. MSB is just the first piece of information. In some formats it's used to define the polarity, but not in all formats...
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Yes, I saw that. He used the DIR9001 as a source for the TDA1541A, but not as a source for his 17bit signed magnitude glue logic. The glue logic he used to interface the DIR9001 with the TDA1541A is not the same glue logic as the one he made for the 17bit DAC.
So the question remains: what did he use as a source for his 17bit signed magnitude glue logic?