so you guys will offer a standalone usb to spdif?
something I could use to feed any dac that accept SPDIF in?
Hi youknowyou,
Yes, this is a universal converter that requires no drivers and can drive any DAC that has S/PDIF input. It supports 44.1/16 ... 96/24 (UAC1). UAC1 uses relatively low frame rate (low interference) with 1ms intervals (1000 frames / second).
If one wants to use S/PDIF coax, one can use the on-board S/PDIF signal to drive a suitable interface. Self powered (battery) operation is also possible. MCK, BCK, DATA and WS signals are present on the board, keep in mind that we use Left Justified data.
We also developed a very clean, battery powered digital audio source to explore the limits of DAC and connected audio equipment and for performing low level measurements.
This very clean source is now available as the UPL16 (44.1/16 and 48/16 support) and the UPL24 (44.1/16 ... 96/24 support). It has Toslink output. Similar to the the UTOS, MCK, BCK, DATA and WS signals (Left Justified) are present on the board.
The two USB sockets on the UPL are for internal battery charging and for firmware updates respectively.
The UPL is based on a single low power micro controller and a S/PDIF transmitter chip. Dynamic master clock scaling is used to reduce interference and power consumption to absolute minimum. The complete UPL24 plus USB stick consume approx. 250 milli watts when streaming 44.1/16. The UPL has an auto power saving mode that puts the UPL in low power mode and switches-off the USB stick power supply.
It supports up to 99 CDs, each CD containing up to 99 tracks (9801 tracks in total) on a single USB stick. Shuffle modes are also provided. USB stick needs to be FAT32 formatted with a MBR. In most cases a new USB stick will work out of the box without formatting. If I am correct, maximum supported USB stick capacity is limited to 2 Terra bytes.
The CDs are represented by folders that have to start with a number between 01 and 99. Within those folders are the WAV tracks that also have to start with a number between 01 and 99. Plain text file called id.txt that holds a number between 1 and 9999 can be added in the root for USB stick identification. Artwork can also be added for reference, but keep in mind that artwork name should not start with a number between 1 and 99.
We only support WAV as this requires no conversion and we can use on-chip hardware instead of software routines. This greatly reduces CPU load and interference levels.
I attached some pictures of the UPL24 and the IR remote control.
Yes, this is a universal converter that requires no drivers and can drive any DAC that has S/PDIF input. It supports 44.1/16 ... 96/24 (UAC1). UAC1 uses relatively low frame rate (low interference) with 1ms intervals (1000 frames / second).
If one wants to use S/PDIF coax, one can use the on-board S/PDIF signal to drive a suitable interface. Self powered (battery) operation is also possible. MCK, BCK, DATA and WS signals are present on the board, keep in mind that we use Left Justified data.
We also developed a very clean, battery powered digital audio source to explore the limits of DAC and connected audio equipment and for performing low level measurements.
This very clean source is now available as the UPL16 (44.1/16 and 48/16 support) and the UPL24 (44.1/16 ... 96/24 support). It has Toslink output. Similar to the the UTOS, MCK, BCK, DATA and WS signals (Left Justified) are present on the board.
The two USB sockets on the UPL are for internal battery charging and for firmware updates respectively.
The UPL is based on a single low power micro controller and a S/PDIF transmitter chip. Dynamic master clock scaling is used to reduce interference and power consumption to absolute minimum. The complete UPL24 plus USB stick consume approx. 250 milli watts when streaming 44.1/16. The UPL has an auto power saving mode that puts the UPL in low power mode and switches-off the USB stick power supply.
It supports up to 99 CDs, each CD containing up to 99 tracks (9801 tracks in total) on a single USB stick. Shuffle modes are also provided. USB stick needs to be FAT32 formatted with a MBR. In most cases a new USB stick will work out of the box without formatting. If I am correct, maximum supported USB stick capacity is limited to 2 Terra bytes.
The CDs are represented by folders that have to start with a number between 01 and 99. Within those folders are the WAV tracks that also have to start with a number between 01 and 99. Plain text file called id.txt that holds a number between 1 and 9999 can be added in the root for USB stick identification. Artwork can also be added for reference, but keep in mind that artwork name should not start with a number between 1 and 99.
We only support WAV as this requires no conversion and we can use on-chip hardware instead of software routines. This greatly reduces CPU load and interference levels.
I attached some pictures of the UPL24 and the IR remote control.
Attachments
I have the UV as well (great DAC) so I'll answer - yes, you can hear small clicks when you use the build in volume control, whether through the remote or through software control.
Best
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Hi hopkins,
On the new MOS DACs I use standard rectangular Toslink inputs. You can see this on the rear view of the MOS16 DAC picture I posted.
I compared real glass fibre (hundred's of very thin glass fibers bundled to a single optical conductor) vs a cheap $1 single plastic fibre optical interlink.
I measured greatly increased phase noise on the Toslink optical receiver output compared to a single plastic fibre.
It turns out that it is impossible to make the hundred's of thin glass fibres exactly the same length (to the nanometer).
So what you get is different light paths, all with a different propagation delay, resulting in timing "noise" as all signals arrive at a slightly different time.
This will change the jitter spectrum by adding random noise. So the audibility of deterministic (data related) jitter spectrum interference is reduced.
So the signal that looks pretty bad on the scope can actually lead to improved sound as deterministic jitter is masked by random jitter. Altman's Jisco system works in a similar way if I am correct.
But things changed a lot since the first CS84xx S/PDIF receivers. Clock recovery is now based on preambles (sync codes in the S/PDIF stream) that are not influenced by the serial audio data. So the PLL gets a much more stable reference signal. PLL circuits also improved over the years and the S/PDIF receiver we use has separate analogue (PLL) and digital power supply pins.
Jitter is usually related to sample timing, if we have a jitter problem we have a sample timing problem. There is just one catch, can we actually hear timing fluctuations in the ps range? no we can't.
The zero order hold output signal of a DAC in combination with timing fluctuations can lead to a PWM effect where the energy level (v * i * t) of each sample can fluctuate so we could end up with timing related bit errors. The higher the weight of the bit, the more impact a given timing fluctuation will have. As long as we don't use any of the MSBs for low level generation we would be fine ..... oh we do use the MSBs for low level generation (MSB trimming remember?).
No wonder we have jitter issues with D/A converters that use the MSBs for low level signal generation.
If we would only use the bits we actually need (only the LSBs for low level signal generation) the audible impact of jitter on a zero order hold signal would be far less.
When generating high level signals using the MSBs these will completely mask low level distortion so it's a non issue here.
Our new MOS DACs are based on a segmented summing converter that only uses the LSBs for low level signals and only the MSBs for high level signals, sample timing problem solved.
What remains is the varying large bandwidth jitter spectrum that may add extra noise. We have to put this interference in quarantine so it won't end up on the DAC output signal. We achieved this using data and bit clock low pass filters between decoder and D/A converter.
The remaining source dependency is mainly related to source interference, not source jitter. We fixed this almost completely by designing a very clean digital audio source, the UPL.
Most audiophile systems destroy the DAC output signal before it even reaches the speaker:
DAC, 5.6Vpp -> volume control -> 100mVpp -> amplification (50x) -> 5Vpp -> speaker.
DAC, software volume control -> 100mVpp -> amplification (50x) -> 5Vpp -> speaker.
The attenuated signal has poor SN ratio and is easily masked by noise so we loose lots of resolution at low listening levels.
With our novel MBL monoblock, following happens with the same listening level:
DAC, 5.6Vpp -> volume control -> 1Vpp -> amplification 5x -> 5Vpp -> speaker
DAC software volume control -> 1Vpp -> amplification 5x -> 5Vpp speaker
We can now use ten times larger signal (improved SN ratio) for the same listening level and get a lot more resolution out of the speaker.
The MBL offers variable gain of x5, x10, and x20.
Why do we have class A and SE amplifiers wasting power? because of audible crossover distortion. The higher the bias current, the less problems we have with the AC voltage generated by the speaker (dynamo).
But there is a more elegant solution to this problem, we applied it in the MBL. The MBL only requires 11 watts or less during idling and sounds at least as smooth as SE or deep class A
I attached some pictures of this MBL monoblock.
On the new MOS DACs I use standard rectangular Toslink inputs. You can see this on the rear view of the MOS16 DAC picture I posted.
I compared real glass fibre (hundred's of very thin glass fibers bundled to a single optical conductor) vs a cheap $1 single plastic fibre optical interlink.
I measured greatly increased phase noise on the Toslink optical receiver output compared to a single plastic fibre.
It turns out that it is impossible to make the hundred's of thin glass fibres exactly the same length (to the nanometer).
So what you get is different light paths, all with a different propagation delay, resulting in timing "noise" as all signals arrive at a slightly different time.
This will change the jitter spectrum by adding random noise. So the audibility of deterministic (data related) jitter spectrum interference is reduced.
So the signal that looks pretty bad on the scope can actually lead to improved sound as deterministic jitter is masked by random jitter. Altman's Jisco system works in a similar way if I am correct.
But things changed a lot since the first CS84xx S/PDIF receivers. Clock recovery is now based on preambles (sync codes in the S/PDIF stream) that are not influenced by the serial audio data. So the PLL gets a much more stable reference signal. PLL circuits also improved over the years and the S/PDIF receiver we use has separate analogue (PLL) and digital power supply pins.
Jitter is usually related to sample timing, if we have a jitter problem we have a sample timing problem. There is just one catch, can we actually hear timing fluctuations in the ps range? no we can't.
The zero order hold output signal of a DAC in combination with timing fluctuations can lead to a PWM effect where the energy level (v * i * t) of each sample can fluctuate so we could end up with timing related bit errors. The higher the weight of the bit, the more impact a given timing fluctuation will have. As long as we don't use any of the MSBs for low level generation we would be fine ..... oh we do use the MSBs for low level generation (MSB trimming remember?).
No wonder we have jitter issues with D/A converters that use the MSBs for low level signal generation.
If we would only use the bits we actually need (only the LSBs for low level signal generation) the audible impact of jitter on a zero order hold signal would be far less.
When generating high level signals using the MSBs these will completely mask low level distortion so it's a non issue here.
Our new MOS DACs are based on a segmented summing converter that only uses the LSBs for low level signals and only the MSBs for high level signals, sample timing problem solved.
What remains is the varying large bandwidth jitter spectrum that may add extra noise. We have to put this interference in quarantine so it won't end up on the DAC output signal. We achieved this using data and bit clock low pass filters between decoder and D/A converter.
The remaining source dependency is mainly related to source interference, not source jitter. We fixed this almost completely by designing a very clean digital audio source, the UPL.
Most audiophile systems destroy the DAC output signal before it even reaches the speaker:
DAC, 5.6Vpp -> volume control -> 100mVpp -> amplification (50x) -> 5Vpp -> speaker.
DAC, software volume control -> 100mVpp -> amplification (50x) -> 5Vpp -> speaker.
The attenuated signal has poor SN ratio and is easily masked by noise so we loose lots of resolution at low listening levels.
With our novel MBL monoblock, following happens with the same listening level:
DAC, 5.6Vpp -> volume control -> 1Vpp -> amplification 5x -> 5Vpp -> speaker
DAC software volume control -> 1Vpp -> amplification 5x -> 5Vpp speaker
We can now use ten times larger signal (improved SN ratio) for the same listening level and get a lot more resolution out of the speaker.
The MBL offers variable gain of x5, x10, and x20.
Why do we have class A and SE amplifiers wasting power? because of audible crossover distortion. The higher the bias current, the less problems we have with the AC voltage generated by the speaker (dynamo).
But there is a more elegant solution to this problem, we applied it in the MBL. The MBL only requires 11 watts or less during idling and sounds at least as smooth as SE or deep class A
I attached some pictures of this MBL monoblock.
Attachments
Thanks. Can you describe the difference, in terms of sound quality, between using with the mirror DAC the UPL as a source versus the usb/toslink converter you developed versus a jittery toslink connection directly from a source (cd player, streamer with toslink out, etc...)? Does the audio source still matter?
Thanks
Thanks
Hi, John
I read this forum since the very beginning. Thank you for sharing you brilliant ideas with us.
Sorry for offtopic, but I have few questions. I planing to build dac with pcm1704, can I use smaller film coupling capacitors in analog part, lets say 10-20uf wima instead of 50uf or 20-40uf insted of 100uf BPO DC? I will use LT3045 voltage regulators
I read this forum since the very beginning. Thank you for sharing you brilliant ideas with us.
Sorry for offtopic, but I have few questions. I planing to build dac with pcm1704, can I use smaller film coupling capacitors in analog part, lets say 10-20uf wima instead of 50uf or 20-40uf insted of 100uf BPO DC? I will use LT3045 voltage regulators
John, thanks for the excellent info, as always.
It makes perfect sense: tda1543 is very sensitive to clocking method and jitter, tda1545 and 1387 less so. The latter use "symmetric offset decoding", which is similar to sign magnitude / segmented summing. BTW, the ad1862 is also done this way.
Thanks,
Alex
It makes perfect sense: tda1543 is very sensitive to clocking method and jitter, tda1545 and 1387 less so. The latter use "symmetric offset decoding", which is similar to sign magnitude / segmented summing. BTW, the ad1862 is also done this way.
Thanks,
Alex
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The AD1862 does not mention Sign Magnitude data format.
It states:
"A serial 20-bit, 2s complement data word is clocked into
the DAC, MSB first, by the external data clock."
So is the conversion done internally?
Hi batteryman,
AD1862 Datasheet page 5
quote:
The design of the AD1862 uses a combination of segmented decoder, R-2R topology and digital offset to produce low distortion at all signal amplitudes. The digital offset technique shifts the midscale output voltage (0 V) away from the MSB transition of the device. Therefore, small amplitude signals are not affected by an MSB change. An extra DAC cell is included to avoid clipping the output at full scale.
AD1862 Datasheet page 5
quote:
The design of the AD1862 uses a combination of segmented decoder, R-2R topology and digital offset to produce low distortion at all signal amplitudes. The digital offset technique shifts the midscale output voltage (0 V) away from the MSB transition of the device. Therefore, small amplitude signals are not affected by an MSB change. An extra DAC cell is included to avoid clipping the output at full scale.
Thanks, I did read that but I didn't think of it as the dac having in effect, converted the TWC input to SM.
I can now answer my own question!
Yes, its 16bit right justifed MSB first. (which explains the distortion although I am surprised I got any audio at all).
To find this out, I installed a sample rate converter evaluation board - a SRC4192 in my dac and connected it to the AD1862 dac board from DIYINHK. (I2S in)
I set the output to I2S and the input to 16bit RJ, and this was the only setting that worked with the dac. (I tried all the other input data formats - I2S, 24bit LJ, 18,20, 24bit RJ)
Taking Marcelvg's advice, I set the 4192's clock generator for 24.576Mhz which gave an output bit clock of about 6.14Mhz and fs of 96k (clock/256) & 20bit compared to the input data of 16bit, 44k/2.822M.
The sound quality is nothing special, with occasional quiet clicks - like a worn LP, but I have not found the cause. Its probably due to the wiring between CD player and dac & maybe the ADUM digital isolator between them or maybe the SRC4192 itself.
This doesn't matter for now as I will be using the AD1820 with a USB to I2S converter and building a second dac powered entirely by Lifepo4 & Lipo cells
using IanCanadas Fifo II and I2S board plus my own balanced TDA1541 dac board.
So I feel a clot for accidentally feeding Ian's I2S board with the wrong data type but in my defence, no one came up with a definitive answer as to what the actual data format was.
You 'live & learn'.
Just validated the bit perfectness of rpi with moode player set to generic hifibery dac using test tracks from lcsaszar and it looks good:
Track1:
Track2:
