sparkle said:how do You set this thing to work properly? I know that I should have 2 volts on input of the i/v and I know that it should be trimmed with VR1 but from which side do You start- from which value of the VR1. Regards
daniel
When you set the I/V stage first time, the TDA1543 is diconnected.
Trim the pot until you have 2,00 volts at the source , than you swich off the supply , and wait for discharge. Than connect the TDA to the I/V stage, power up both circuits and do the final trimming.
Re: Re: Balnced Arrangement
Reclock: first off , do you think I need 2 FF in series to do the reclock? or just one in sinchronous mode?
No inverters, no buffers? You know , it is just fiew days that the XOR buffers are working in the circuits and every time I change something in the set up is like to jump off the spring-board
And jitter is so underhand
What is the way of inverting clock? I re read your .pdf for the split LR version I admit it is interesting to me and I feel like I am close to the possibilty of making an effort like that, if you have a pcb of your work I will be interested for sure
guido said:
Two idea's for improvements:
reclock all the data with FF's: use '74 so you don't need inverters and reclock with the tentclock. You will loose jitter created by the 7310 (don't know the timingrelation between 7310 I2S out and it's clock input but it should be possible). Maybe you need to invert the clock to the 7310.
Second, obvious (coming from me
I2S streams and use one dac for left and one for right.
Greetings,
Reclock: first off , do you think I need 2 FF in series to do the reclock? or just one in sinchronous mode?
No inverters, no buffers? You know , it is just fiew days that the XOR buffers are working in the circuits and every time I change something in the set up is like to jump off the spring-board
And jitter is so underhand
What is the way of inverting clock? I re read your .pdf for the split LR version I admit it is interesting to me and I feel like I am close to the possibilty of making an effort like that, if you have a pcb of your work I will be interested for sure
HI!
Mr. Billiani - thanks You made my day .
I was allways wondering how to trim the active i/v ......none of my question were answered until now. Thanks again!
regards
daniel
edit:
HBarske- I can't see that You are using volume control like in d! service manual- if so- what is the maksimum output that You get out of it?
Mr. Billiani - thanks You made my day
.I was allways wondering how to trim the active i/v ......none of my question were answered until now. Thanks again!
regards
daniel
edit:
HBarske- I can't see that You are using volume control like in d! service manual- if so- what is the maksimum output that You get out of it?
You are not wrong if we are using for instance TDA1541 but in case of TDA1543 and TDA1545 we need something in the positive side (2V or little more for the 1543 and littl more for 1545) it is all said at few first posts of this thread. Or am I wrong now?
Also the output voltage for measuring is taken fron pin 6 and 8 of the TDA1543 and between ground. Pin 7 (Vref) stays in the air (not connected). Correct me if I made a mistake, please.
regards
daniel
Also the output voltage for measuring is taken fron pin 6 and 8 of the TDA1543 and between ground. Pin 7 (Vref) stays in the air (not connected). Correct me if I made a mistake, please.
regards
daniel
sparkle said:You are not wrong if we are using for instance TDA1541 but in case of TDA1543 and TDA1545 we need something in the positive side (2V or little more for the 1543 and littl more for 1545) it is all said at few first posts of this thread. Or am I wrong now?
Also the output voltage for measuring is taken fron pin 6 and 8 of the TDA1543 and between ground. Pin 7 (Vref) stays in the air (not connected). Correct me if I made a mistake, please.
regards
daniel
Daniel,
once you set the circuit as I suggested above is possible to trim the pot till the Voutput(at the source of D1) is EQUAL to Vref -as HBarske suggested. This voltage varies slightly from chip to chip and is around 2._ _volts.It seems to me a good idea.
Oh boy!
I have sommething to learn
.
O.k. I got it now.
Mr. Billiani I got the way to trim and with the other post in this thread it would be like walking on a ground to trim it. Sorry for my easy questions if they did bother You but I have really much to learn and the forum is the place where I can ask.
Thanks
will try that I/V and look forward for a new posts on this thread
regards
daniel
I have sommething to learn
.O.k. I got it now.
Mr. Billiani I got the way to trim and with the other post in this thread it would be like walking on a ground to trim it. Sorry for my easy questions if they did bother You but I have really much to learn and the forum is the place where I can ask.
Thanks
will try that I/V and look forward for a new posts on this thread
regards
daniel
nar said:So guys has someone succeeded in adapting the circuit to the 1545 ?
Should sound nice ....
The only big difference between the implementation around the output sections of these DACs is the different full-scale current, which is lower for the 1545.
Increasing the 680R to compensate the voltage difference should be just fine.
Cheers
Andrea
Re: Re: Re: Balnced Arrangement
Back to digital.
One FF should do it, i think but you need to look carefull at the timing between the master clock in and the output of the 7310 I2S. It should not happen that the FF inputs are changing state at the same time as the FF is clocking the data. So you might need an inverter in the clock towards 7310.
If you use '74 FF it will do the inversion for you: it has normal and inverted output! But then you need two of them for the three i2s lines. Or use one inverter chip and e.g. '174 FF.
About the splitting, there are two guys posting that they are doing this with bigger prog. logic. Only one chip then, but many small smd pens.
PCB can be bought, but further improvements can be made to the reclocking (not to mention the DAC side of things): still need to modify the GAL so I2S-clock is also latched output and then clock the FF in the GAL with inverted 11MHz clock: jitter of '161 removed
mvg,
stefanobilliani said:
Reclock: first off , do you think I need 2 FF in series to do the reclock? or just one in sinchronous mode?
No inverters, no buffers? You know , it is just fiew days that the XOR buffers are working in the circuits and every time I change something in the set up is like to jump off the spring-board
And jitter is so underhand
What is the way of inverting clock? I re read your .pdf for the split LR version I admit it is interesting to me and I feel like I am close to the possibilty of making an effort like that, if you have a pcb of your work I will be interested for sure
Back to digital.
One FF should do it, i think but you need to look carefull at the timing between the master clock in and the output of the 7310 I2S. It should not happen that the FF inputs are changing state at the same time as the FF is clocking the data. So you might need an inverter in the clock towards 7310.
If you use '74 FF it will do the inversion for you: it has normal and inverted output! But then you need two of them for the three i2s lines. Or use one inverter chip and e.g. '174 FF.
About the splitting, there are two guys posting that they are doing this with bigger prog. logic. Only one chip then, but many small smd pens.
PCB can be bought, but further improvements can be made to the reclocking (not to mention the DAC side of things): still need to modify the GAL so I2S-clock is also latched output and then clock the FF in the GAL with inverted 11MHz clock: jitter of '161 removed
mvg,
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