Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter - Page 98 - diyAudio
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Old 12th September 2012, 05:27 PM   #971
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Quote:
Originally Posted by vzs View Post
Agree that would be a nice adding for a future rev. clock board.
I'm talking about the FFC cable, right to the 7pin PH2 cable. Afaik this carries the MCK from clock board to fifo and the power from fifo to clock, and probably other signals as well... Ian could tell.

This small adapter could fit/float between the FIFO and Clock-board and would have all connectors needed 2x 7pin PH2, 2x FFC conn and 2x PH2 con for power (right-angled smd version to be neat). I'm working on my multibit DAC board now and with one dirty hand I will do this as well - just to decide which digital coupler to use.
For MCLK, there is not any problem. The only thing I'm concerned about would be the 12-18ns propagation delay. As well as the 3ns channel skew. The I2S re-clock can't be done within one mclk phase. The total delay will be around 3 clk time for 98.xxx MHz. Risk of low Tsu and unstable. But if we don't care much about the jitter on I2S....

Ian
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Old 12th September 2012, 05:45 PM   #972
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Originally Posted by glt View Post
I think the NVE IL715 is a good part. It is used in other implementations to isolate I2S. I did an experiment here: Experiments with NVE IL715 Isolator H i F i D U I N O
Did you try Si8440? Different from GMR , similar to TI, it use high voltage CMOS capacitive gap technology, and runs at 150MHz. It might share same footprint with IL715.

Ian
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Old 12th September 2012, 05:49 PM   #973
qusp is offline qusp  Australia
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maybe its better to just isolate the i2s input? though I do like the idea of isolating everything up to the last reclock
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Old 12th September 2012, 06:17 PM   #974
asaf23 is offline asaf23  Russian Federation
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Meanwhile I will try the following approach to isolate PC noise from the DAC (see attached file). Hope the Ian's FIFO will take care with the some added by GMR jitter
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File Type: pdf flow_chart.pdf (178.7 KB, 93 views)
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Old 12th September 2012, 06:22 PM   #975
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Originally Posted by qusp View Post
maybe its better to just isolate the i2s input? though I do like the idea of isolating everything up to the last reclock
It might be OK for high MCLK around 100MHz, if there is anything wrong caused by low Tsu, it should be corrceted by the last flip-flop at next raising edge. But I have to confirm this at a real circuit board to see if could pass the loop test.

Ian
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Old 12th September 2012, 06:30 PM   #976
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Originally Posted by asaf23 View Post
Meanwhile I will try the following approach to isolate PC noise from the DAC (see attached file). Hope the Ian's FIFO will take care with the some added by GMR jitter
Awesome project.

Yes, FIFO will take care jitter before it if all data are keeping correct.

Ian
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Old 12th September 2012, 07:11 PM   #977
Zoran is offline Zoran  Serbia
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I use TX & RX ballanced line for I2S
(asaf23 made a diagram...)
no need for sheilded cable just twisted pairs
and signal is much better from the point of integrity
also using isolated I2S bus and MCK, with AD units
but with galvanicaly separated power supply. Every isolated module have to have own
power from transformer point...
.
Some devices are do not accept USB galvanic isolation
but My exeriaence is that USB power should be used just like the info is the device are plugged in.
.
The Q of the transformers remains, I am using C.T. types full rect. So every ground is "real", but I didnt try with more common PS design?
.
The story of the jitter is not crucial thing, because it is about mesuremens with very expensive equipment and operating with proper knowledge how to use the eqip.
so for me it is in apsence of meas - just try it one to one...
There are more vital things in design prior to famous jitter issues, at least for me.
.
cheers
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Old 12th September 2012, 11:48 PM   #978
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Quote:
Originally Posted by vzs View Post
Agree that would be a nice adding for a future rev. clock board.
I'm talking about the FFC cable, right to the 7pin PH2 cable. Afaik this carries the MCK from clock board to fifo and the power from fifo to clock, and probably other signals as well... Ian could tell.

This small adapter could fit/float between the FIFO and Clock-board and would have all connectors needed 2x 7pin PH2, 2x FFC conn and 2x PH2 con for power (right-angled smd version to be neat). I'm working on my multibit DAC board now and with one dirty hand I will do this as well - just to decide which digital coupler to use.
It's achievable. Will take into consideration.

Ian
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Old 13th September 2012, 04:36 AM   #979
glt is offline glt  United States
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Quote:
Originally Posted by iancanada View Post
Did you try Si8440? Different from GMR , similar to TI, it use high voltage CMOS capacitive gap technology, and runs at 150MHz. It might share same footprint with IL715.

Ian
I did not try the Si8440 primarily because per spec it had more added jitter than the NVE part. In addition, most implementations uses the NVE isolator.
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Old 15th September 2012, 05:42 PM   #980
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Default Digital isolator board for FIFO KIT

A small digital isolator board, providing 100% isolation between FIFO board and clock board. Making the clock board works as a local part of DAC with all EMI noise isolated from digital front end.

The Fmax could go up to 110MHz with IL260E or 150MHz with Si8650.

It can stack on top of the FIFO board, or to be the base of the clock board.

Have a nice weekend

Ian
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File Type: jpg ISOLATORPCB.jpg (71.7 KB, 438 views)
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